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[PULL v1 10/14] target/microblaze: Add MFS Rd,EDR translation
From: |
Edgar E. Iglesias |
Subject: |
[PULL v1 10/14] target/microblaze: Add MFS Rd,EDR translation |
Date: |
Thu, 14 May 2020 16:13:58 +0200 |
From: Tong Ho <address@hidden>
This is to fix cpu-abort with 'qemu: fatal: unknown mfs reg d'
(in the default case) when microblaze guest issues 'MFS Rd,EDR'
instruction.
Since embeddedsw release 2019.2, XPlm_ExceptionHandler() issues
the instruction on exception, and microblaze model aborts when
PLM firmware guest encounters an exception.
Signed-off-by: Tong Ho <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 20b7427811..92b3630804 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -581,6 +581,7 @@ static void dec_msr(DisasContext *dc)
case SR_ESR:
case SR_FSR:
case SR_BTR:
+ case SR_EDR:
tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_SR[sr]);
break;
case 0x800:
--
2.20.1
- [PULL v1 00/14] Xilinx queue 2020-05-14, Edgar E. Iglesias, 2020/05/14
- [PULL v1 01/14] hw/net/xilinx_axienet: Auto-clear PHY Autoneg, Edgar E. Iglesias, 2020/05/14
- [PULL v1 02/14] hw/net/xilinx_axienet: Cleanup stream->push assignment, Edgar E. Iglesias, 2020/05/14
- [PULL v1 03/14] hw/net/xilinx_axienet: Remove unncessary cast, Edgar E. Iglesias, 2020/05/14
- [PULL v1 05/14] hw/core: stream: Add an end-of-packet flag, Edgar E. Iglesias, 2020/05/14
- [PULL v1 06/14] hw/net/xilinx_axienet: Handle fragmented packets from DMA, Edgar E. Iglesias, 2020/05/14
- [PULL v1 04/14] hw/dma/xilinx_axidma: Add DMA memory-region property, Edgar E. Iglesias, 2020/05/14
- [PULL v1 07/14] hw/dma/xilinx_axidma: mm2s: Stream descriptor by descriptor, Edgar E. Iglesias, 2020/05/14
- [PULL v1 08/14] hw/dma/xilinx_axidma: s2mm: Support stream fragments, Edgar E. Iglesias, 2020/05/14
- [PULL v1 09/14] MAINTAINERS: Add myself as streams maintainer, Edgar E. Iglesias, 2020/05/14
- [PULL v1 10/14] target/microblaze: Add MFS Rd,EDR translation,
Edgar E. Iglesias <=
- [PULL v1 11/14] target/microblaze: Fix FPU2 instruction check, Edgar E. Iglesias, 2020/05/14
- [PULL v1 12/14] target/microblaze: gdb: Extend the number of registers presented to GDB, Edgar E. Iglesias, 2020/05/14
- [PULL v1 13/14] target/microblaze: gdb: Fix incorrect SReg reporting, Edgar E. Iglesias, 2020/05/14
- [PULL v1 14/14] target/microblaze: monitor: Increase the number of registers reported, Edgar E. Iglesias, 2020/05/14
- Re: [PULL v1 00/14] Xilinx queue 2020-05-14, Peter Maydell, 2020/05/14