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[Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs
From: |
Heiko Sieger |
Subject: |
[Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs |
Date: |
Wed, 20 May 2020 21:47:33 -0000 |
Jan, I tried your suggestion but it didn't make a difference. Here is my
current setup:
h/w: AMD Ryzen 9 3900X
kernel: 5.4
QEMU: 5.0.0-6
Chipset selection: Q35-5.0
Configuration: host-passthrough, cache enabled
Use CoreInfo.exe inside Windows. The problem is this:
Logical Processor to Cache Map:
**---------------------- Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**---------------------- Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize
64
**---------------------- Unified Cache 0, Level 2, 512 KB, Assoc 8, LineSize 64
********---------------- Unified Cache 1, Level 3, 16 MB, Assoc 16, LineSize 64
The last line above should be as follows:
******------------------ Unified Cache 0, Level 3, 16 MB, Assoc 16,
LineSize 64
The cache is supposed to be associated with 3 cores a 2 threads in group
0. Yet it shows 8 (2x4) vcpus inside a cache that is associated with the
next group.
In total, I always get 3 L3 caches instead of 4 L4 caches for my 12
cores / 24 threads. Also see my next post.
--
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https://bugs.launchpad.net/bugs/1856335
Title:
Cache Layout wrong on many Zen Arch CPUs
Status in QEMU:
New
Bug description:
AMD CPUs have L3 cache per 2, 3 or 4 cores. Currently, TOPOEXT seems
to always map Cache ass if it was an 4-Core per CCX CPU, which is
incorrect, and costs upwards 30% performance (more realistically 10%)
in L3 Cache Layout aware applications.
Example on a 4-CCX CPU (1950X /w 8 Cores and no SMT):
<cpu mode='custom' match='exact' check='full'>
<model fallback='forbid'>EPYC-IBPB</model>
<vendor>AMD</vendor>
<topology sockets='1' cores='8' threads='1'/>
In windows, coreinfo reports correctly:
****---- Unified Cache 1, Level 3, 8 MB, Assoc 16, LineSize 64
----**** Unified Cache 6, Level 3, 8 MB, Assoc 16, LineSize 64
On a 3-CCX CPU (3960X /w 6 cores and no SMT):
<cpu mode='custom' match='exact' check='full'>
<model fallback='forbid'>EPYC-IBPB</model>
<vendor>AMD</vendor>
<topology sockets='1' cores='6' threads='1'/>
in windows, coreinfo reports incorrectly:
****-- Unified Cache 1, Level 3, 8 MB, Assoc 16, LineSize 64
----** Unified Cache 6, Level 3, 8 MB, Assoc 16, LineSize 64
Validated against 3.0, 3.1, 4.1 and 4.2 versions of qemu-kvm.
With newer Qemu there is a fix (that does behave correctly) in using the dies
parameter:
<qemu:arg value='cores=3,threads=1,dies=2,sockets=1'/>
The problem is that the dies are exposed differently than how AMD does
it natively, they are exposed to Windows as sockets, which means, that
if you are nto a business user, you can't ever have a machine with
more than two CCX (6 cores) as consumer versions of Windows only
supports two sockets. (Should this be reported as a separate bug?)
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- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, (continued)
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Jan Klos, 2020/05/15
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Damir, 2020/05/15
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Babu Moger, 2020/05/15
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Jan Klos, 2020/05/17
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Jan Klos, 2020/05/17
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/18
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Babu Moger, 2020/05/18
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/18
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Jan Klos, 2020/05/19
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/19
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs,
Heiko Sieger <=
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/20
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Jan Klos, 2020/05/21
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/24
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/29