[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v8 01/62] target/riscv: add vector extension field in CPURISCVSta
From: |
LIU Zhiwei |
Subject: |
[PATCH v8 01/62] target/riscv: add vector extension field in CPURISCVState |
Date: |
Thu, 21 May 2020 17:43:12 +0800 |
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/riscv/cpu.h | 12 ++++++++++++
target/riscv/translate.c | 3 ++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d0e7f5b9c5..7452c6e118 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -65,6 +65,7 @@
#define RVA RV('A')
#define RVF RV('F')
#define RVD RV('D')
+#define RVV RV('V')
#define RVC RV('C')
#define RVS RV('S')
#define RVU RV('U')
@@ -95,9 +96,20 @@ typedef struct CPURISCVState CPURISCVState;
#include "pmp.h"
+#define RV_VLEN_MAX 512
+
struct CPURISCVState {
target_ulong gpr[32];
uint64_t fpr[32]; /* assume both F and D extensions */
+
+ /* vector coprocessor state. */
+ uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
+ target_ulong vxrm;
+ target_ulong vxsat;
+ target_ulong vl;
+ target_ulong vstart;
+ target_ulong vtype;
+
target_ulong pc;
target_ulong load_res;
target_ulong load_val;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 43bf7e39a6..b71b7e4bc2 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -32,7 +32,7 @@
#include "instmap.h"
/* global register indices */
-static TCGv cpu_gpr[32], cpu_pc;
+static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
@@ -886,6 +886,7 @@ void riscv_translate_init(void)
}
cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc");
+ cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl");
load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res),
"load_res");
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
--
2.23.0
- [PATCH v8 00/62] target/riscv: support vector extension v0.7.1, LIU Zhiwei, 2020/05/21
- [PATCH v8 00/62] target/riscv: support vector extension v0.7.1, LIU Zhiwei, 2020/05/21
- [PATCH v8 01/62] target/riscv: add vector extension field in CPURISCVState,
LIU Zhiwei <=
- [PATCH v8 02/62] target/riscv: implementation-defined constant parameters, LIU Zhiwei, 2020/05/21
- [PATCH v8 03/62] target/riscv: support vector extension csr, LIU Zhiwei, 2020/05/21
- [PATCH v8 04/62] target/riscv: add vector configure instruction, LIU Zhiwei, 2020/05/21
- [PATCH v8 05/62] target/riscv: add an internals.h header, LIU Zhiwei, 2020/05/21
- [PATCH v8 06/62] target/riscv: add vector stride load and store instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 07/62] target/riscv: add vector index load and store instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 08/62] target/riscv: add fault-only-first unit stride load, LIU Zhiwei, 2020/05/21
- [PATCH v8 09/62] target/riscv: add vector amo operations, LIU Zhiwei, 2020/05/21
- [PATCH v8 10/62] target/riscv: vector single-width integer add and subtract, LIU Zhiwei, 2020/05/21
- [PATCH v8 11/62] target/riscv: vector widening integer add and subtract, LIU Zhiwei, 2020/05/21