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[PULL 066/115] x86/cpu: Enable AVX512_VP2INTERSECT cpu feature
From: |
Paolo Bonzini |
Subject: |
[PULL 066/115] x86/cpu: Enable AVX512_VP2INTERSECT cpu feature |
Date: |
Thu, 11 Jun 2020 15:44:00 -0400 |
From: Cathy Zhang <cathy.zhang@intel.com>
AVX512_VP2INTERSECT compute vector pair intersection to a pair
of mask registers, which is introduced with intel Tiger Lake,
defining as CPUID.(EAX=7,ECX=0):EDX[bit 08].
Refer to the following release spec:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
Message-Id: <1586760758-13638-1-git-send-email-cathy.zhang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b5705cda86..e89d9fa894 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -985,7 +985,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.feat_names = {
NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
NULL, NULL, NULL, NULL,
- NULL, NULL, "md-clear", NULL,
+ "avx512-vp2intersect", NULL, "md-clear", NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL /* pconfig */, NULL,
NULL, NULL, NULL, NULL,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 37572bd437..100476ee89 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -772,6 +772,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
/* AVX512 Multiply Accumulation Single Precision */
#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
+/* AVX512 Vector Pair Intersection to a Pair of Mask Registers */
+#define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
/* Speculation Control */
#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
/* Single Thread Indirect Branch Predictors */
--
2.26.2
- [PULL 054/115] target/i386: fix fscale handling of infinite exponents, (continued)
- [PULL 054/115] target/i386: fix fscale handling of infinite exponents, Paolo Bonzini, 2020/06/11
- [PULL 044/115] qom/container: remove .instance_size initializer from container_info, Paolo Bonzini, 2020/06/11
- [PULL 037/115] hw/i386/vmport: Add support for CMD_GETHZ, Paolo Bonzini, 2020/06/11
- [PULL 045/115] cpus: Fix botched configure_icount() error API violation fix, Paolo Bonzini, 2020/06/11
- [PULL 041/115] qom/object: factor out the initialization of hash table of properties, Paolo Bonzini, 2020/06/11
- [PULL 055/115] target/i386: fix fscale handling of rounding precision, Paolo Bonzini, 2020/06/11
- [PULL 059/115] hw/elf_ops: Do not ignore write failures when loading ELF, Paolo Bonzini, 2020/06/11
- [PULL 025/115] hw/i386/vmport: Add reference to VMware open-vm-tools, Paolo Bonzini, 2020/06/11
- [PULL 017/115] hyperv: expose API to determine if synic is enabled, Paolo Bonzini, 2020/06/11
- [PULL 014/115] qom/object: Move Object typedef to 'qemu/typedefs.h', Paolo Bonzini, 2020/06/11
- [PULL 066/115] x86/cpu: Enable AVX512_VP2INTERSECT cpu feature,
Paolo Bonzini <=
- [PULL 067/115] vfio/pci: Use kvm_irqchip_add_irqfd_notifier_gsi() for irqfds, Paolo Bonzini, 2020/06/11
- [PULL 035/115] hw/i386/vmport: Allow x2apic without IR, Paolo Bonzini, 2020/06/11
- [PULL 030/115] hw/i386/vmport: Report vmware-vmx-type in CMD_GETVERSION, Paolo Bonzini, 2020/06/11
- [PULL 064/115] target/i386: fix fisttpl, fisttpll handling of out-of-range values, Paolo Bonzini, 2020/06/11
- [PULL 024/115] target/i386: fix phadd* with identical destination and source register, Paolo Bonzini, 2020/06/11
- [PULL 048/115] megasas: use unsigned type for reply_queue_head and check index, Paolo Bonzini, 2020/06/11
- [PULL 060/115] target/i386: fix floating-point load-constant rounding, Paolo Bonzini, 2020/06/11
- [PULL 019/115] vmbus: vmbus implementation, Paolo Bonzini, 2020/06/11
- [PULL 022/115] vmbus: add infrastructure to save/load vmbus requests, Paolo Bonzini, 2020/06/11
- [PULL 057/115] exec: Propagate cpu_memory_rw_debug() error, Paolo Bonzini, 2020/06/11