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Re: [PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries
From: |
Alistair Francis |
Subject: |
Re: [PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries |
Date: |
Mon, 15 Jun 2020 12:04:32 -0700 |
On Mon, Jun 8, 2020 at 7:26 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Move the flash and DRAM to the end of the SoC memmap table.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index f64aa52..c94ff6f 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -80,10 +80,10 @@ static const struct MemmapEntry {
> [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
> [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
> [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
> - [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
> - [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
> [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
> [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
> + [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
> + [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
> };
>
> #define OTP_SERIAL 1
> --
> 2.7.4
>
>
- Re: [PATCH 08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs, (continued)
- [PATCH 07/15] hw/riscv: sifive_u: Hook a GPIO controller, Bin Meng, 2020/06/08
- [PATCH 10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name, Bin Meng, 2020/06/08
- [PATCH 09/15] hw/riscv: sifive_u: Add reset functionality, Bin Meng, 2020/06/08
- [PATCH 12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004, Bin Meng, 2020/06/08
- [PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries, Bin Meng, 2020/06/08
- Re: [PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries,
Alistair Francis <=
- [PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state, Bin Meng, 2020/06/08
- [PATCH 13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state, Bin Meng, 2020/06/08
- [PATCH 15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device, Bin Meng, 2020/06/08
- Re: [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support, Alistair Francis, 2020/06/15