[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 4/5] hw/riscv: sifive_u: Sort the SoC memmap table entries
From: |
Bin Meng |
Subject: |
[PATCH v2 4/5] hw/riscv: sifive_u: Sort the SoC memmap table entries |
Date: |
Mon, 15 Jun 2020 17:50:40 -0700 |
From: Bin Meng <bin.meng@windriver.com>
Move the flash and DRAM to the end of the SoC memmap table.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
hw/riscv/sifive_u.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f64aa52..c94ff6f 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -80,10 +80,10 @@ static const struct MemmapEntry {
[SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
[SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
[SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
- [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
- [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
[SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
[SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
+ [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
+ [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
};
#define OTP_SERIAL 1
--
2.7.4
[PATCH v2 3/5] hw/riscv: sifive_u: Support different boot source per MSEL pin state, Bin Meng, 2020/06/15
[PATCH v2 4/5] hw/riscv: sifive_u: Sort the SoC memmap table entries,
Bin Meng <=
[PATCH v2 5/5] hw/riscv: sifive_u: Add a dummy DDR memory controller device, Bin Meng, 2020/06/15
Re: [PATCH v2 0/5] hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support, Alistair Francis, 2020/06/16