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[PULL 12/33] net: cadence_gem: Fix the queue address update during wrap
From: |
Jason Wang |
Subject: |
[PULL 12/33] net: cadence_gem: Fix the queue address update during wrap around |
Date: |
Tue, 16 Jun 2020 14:45:23 +0800 |
From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
During wrap around and reset, queues are pointing to initial base
address of queue 0, irrespective of what queue we are dealing with.
Fix it by assigning proper base address every time.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
---
hw/net/cadence_gem.c | 37 +++++++++++++++++++++++++++++++++----
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 2e273dca..fd3e4a8 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -845,6 +845,35 @@ static int get_queue_from_screen(CadenceGEMState *s,
uint8_t *rxbuf_ptr,
return 0;
}
+static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q)
+{
+ uint32_t base_addr = 0;
+
+ switch (q) {
+ case 0:
+ base_addr = s->regs[tx ? GEM_TXQBASE : GEM_RXQBASE];
+ break;
+ case 1 ... (MAX_PRIORITY_QUEUES - 1):
+ base_addr = s->regs[(tx ? GEM_TRANSMIT_Q1_PTR :
+ GEM_RECEIVE_Q1_PTR) + q - 1];
+ break;
+ default:
+ g_assert_not_reached();
+ };
+
+ return base_addr;
+}
+
+static inline uint32_t gem_get_tx_queue_base_addr(CadenceGEMState *s, int q)
+{
+ return gem_get_queue_base_addr(s, true, q);
+}
+
+static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q)
+{
+ return gem_get_queue_base_addr(s, false, q);
+}
+
static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q)
{
hwaddr desc_addr = 0;
@@ -1043,7 +1072,7 @@ static ssize_t gem_receive(NetClientState *nc, const
uint8_t *buf, size_t size)
/* Next descriptor */
if (rx_desc_get_wrap(s->rx_desc[q])) {
DB_PRINT("wrapping RX descriptor list\n");
- s->rx_desc_addr[q] = s->regs[GEM_RXQBASE];
+ s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q);
} else {
DB_PRINT("incrementing RX descriptor list\n");
s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true);
@@ -1199,7 +1228,7 @@ static void gem_transmit(CadenceGEMState *s)
sizeof(desc_first));
/* Advance the hardware current descriptor past this packet */
if (tx_desc_get_wrap(desc)) {
- s->tx_desc_addr[q] = s->regs[GEM_TXQBASE];
+ s->tx_desc_addr[q] = gem_get_tx_queue_base_addr(s, q);
} else {
s->tx_desc_addr[q] = packet_desc_addr +
4 * gem_get_desc_len(s, false);
@@ -1251,7 +1280,7 @@ static void gem_transmit(CadenceGEMState *s)
} else {
packet_desc_addr = 0;
}
- packet_desc_addr |= s->regs[GEM_TXQBASE];
+ packet_desc_addr |= gem_get_tx_queue_base_addr(s, q);
} else {
packet_desc_addr += 4 * gem_get_desc_len(s, false);
}
@@ -1457,7 +1486,7 @@ static void gem_write(void *opaque, hwaddr offset,
uint64_t val,
if (!(val & GEM_NWCTRL_TXENA)) {
/* Reset to start of Q when transmit disabled. */
for (i = 0; i < s->num_priority_queues; i++) {
- s->tx_desc_addr[i] = s->regs[GEM_TXQBASE];
+ s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i);
}
}
if (gem_can_receive(qemu_get_queue(s->nic))) {
--
2.5.0
- [PULL 03/33] tap: allow extended virtio header with hash info, (continued)
- [PULL 03/33] tap: allow extended virtio header with hash info, Jason Wang, 2020/06/16
- [PULL 02/33] virtio-net: implement RX RSS processing, Jason Wang, 2020/06/16
- [PULL 06/33] virtio-net: add migration support for RSS and hash report, Jason Wang, 2020/06/16
- [PULL 07/33] virtio-net: align RSC fields with updated virtio-net header, Jason Wang, 2020/06/16
- [PULL 09/33] hw/net/tulip: Fix 'Descriptor Error' definition, Jason Wang, 2020/06/16
- [PULL 10/33] hw/net/tulip: Log descriptor overflows, Jason Wang, 2020/06/16
- [PULL 08/33] Fix tulip breakage, Jason Wang, 2020/06/16
- [PULL 11/33] net: cadence_gem: Fix debug statements, Jason Wang, 2020/06/16
- [PULL 16/33] net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState, Jason Wang, 2020/06/16
- [PULL 14/33] net: cadence_gem: Define access permission for interrupt registers, Jason Wang, 2020/06/16
- [PULL 12/33] net: cadence_gem: Fix the queue address update during wrap around,
Jason Wang <=
- [PULL 13/33] net: cadence_gem: Fix irq update w.r.t queue, Jason Wang, 2020/06/16
- [PULL 15/33] net: cadence_gem: Set ISR according to queue in use, Jason Wang, 2020/06/16
- [PULL 17/33] net: cadence_gem: Fix up code style, Jason Wang, 2020/06/16
- [PULL 18/33] net: cadence_gem: Add support for jumbo frames, Jason Wang, 2020/06/16
- [PULL 19/33] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg, Jason Wang, 2020/06/16
- [PULL 20/33] net: cadence_gem: Update the reset value for interrupt mask register, Jason Wang, 2020/06/16
- [PULL 22/33] net: cadence_gem: Fix RX address filtering, Jason Wang, 2020/06/16
- [PULL 21/33] net: cadence_gem: TX_LAST bit should be set by guest, Jason Wang, 2020/06/16
- [PULL 23/33] net: use peer when purging queue in qemu_flush_or_purge_queue_packets(), Jason Wang, 2020/06/16
- [PULL 24/33] net/colo-compare.c: Create event_bh with the right AioContext, Jason Wang, 2020/06/16