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[PATCH 16/21] target/arm: Convert Neon 2-reg-misc fp-compare-with-zero i
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From: |
Peter Maydell |
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Subject: |
[PATCH 16/21] target/arm: Convert Neon 2-reg-misc fp-compare-with-zero insns to decodetree |
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Date: |
Tue, 16 Jun 2020 18:08:39 +0100 |
Convert the fp-compare-with-zero insns in the Neon 2-reg-misc group to
decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/neon-dp.decode | 6 ++++
target/arm/translate-neon.inc.c | 28 ++++++++++++++++++
target/arm/translate.c | 50 ++++-----------------------------
3 files changed, 39 insertions(+), 45 deletions(-)
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index ea8d5fd99c3..c9acd00f1e8 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -479,6 +479,12 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 .
op:1 1 .... @1reg_imm
VABS 1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc
VNEG 1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc
+ VCGT0_F 1111 001 11 . 11 .. 01 .... 0 1000 . . 0 .... @2misc
+ VCGE0_F 1111 001 11 . 11 .. 01 .... 0 1001 . . 0 .... @2misc
+ VCEQ0_F 1111 001 11 . 11 .. 01 .... 0 1010 . . 0 .... @2misc
+ VCLE0_F 1111 001 11 . 11 .. 01 .... 0 1011 . . 0 .... @2misc
+ VCLT0_F 1111 001 11 . 11 .. 01 .... 0 1100 . . 0 .... @2misc
+
VABS_F 1111 001 11 . 11 .. 01 .... 0 1110 . . 0 .... @2misc
VNEG_F 1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index ab183e47d7d..a62da21b152 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -3768,3 +3768,31 @@ static bool trans_VRINTX(DisasContext *s, arg_2misc *a)
}
return do_2misc_fp(s, a, gen_helper_rints_exact);
}
+
+#define WRAP_FP_CMP0_FWD(WRAPNAME, FUNC) \
+ static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \
+ { \
+ TCGv_i32 zero = tcg_const_i32(0); \
+ FUNC(d, m, zero, fpst); \
+ tcg_temp_free_i32(zero); \
+ }
+#define WRAP_FP_CMP0_REV(WRAPNAME, FUNC) \
+ static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \
+ { \
+ TCGv_i32 zero = tcg_const_i32(0); \
+ FUNC(d, zero, m, fpst); \
+ tcg_temp_free_i32(zero); \
+ }
+
+#define DO_FP_CMP0(INSN, FUNC, REV) \
+ WRAP_FP_CMP0_##REV(gen_##INSN, FUNC) \
+ static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
+ { \
+ return do_2misc_fp(s, a, gen_##INSN); \
+ }
+
+DO_FP_CMP0(VCGT0_F, gen_helper_neon_cgt_f32, FWD)
+DO_FP_CMP0(VCGE0_F, gen_helper_neon_cge_f32, FWD)
+DO_FP_CMP0(VCEQ0_F, gen_helper_neon_ceq_f32, FWD)
+DO_FP_CMP0(VCLE0_F, gen_helper_neon_cge_f32, REV)
+DO_FP_CMP0(VCLT0_F, gen_helper_neon_cgt_f32, REV)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 48377860c75..dc98928856d 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4954,6 +4954,11 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
case NEON_2RM_VCVT_SF:
case NEON_2RM_VCVT_UF:
case NEON_2RM_VRINTX:
+ case NEON_2RM_VCGT0_F:
+ case NEON_2RM_VCGE0_F:
+ case NEON_2RM_VCEQ0_F:
+ case NEON_2RM_VCLE0_F:
+ case NEON_2RM_VCLT0_F:
/* handled by decodetree */
return 1;
case NEON_2RM_VTRN:
@@ -4975,51 +4980,6 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
for (pass = 0; pass < (q ? 4 : 2); pass++) {
tmp = neon_load_reg(rm, pass);
switch (op) {
- case NEON_2RM_VCGT0_F:
- {
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
- tmp2 = tcg_const_i32(0);
- gen_helper_neon_cgt_f32(tmp, tmp, tmp2, fpstatus);
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_ptr(fpstatus);
- break;
- }
- case NEON_2RM_VCGE0_F:
- {
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
- tmp2 = tcg_const_i32(0);
- gen_helper_neon_cge_f32(tmp, tmp, tmp2, fpstatus);
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_ptr(fpstatus);
- break;
- }
- case NEON_2RM_VCEQ0_F:
- {
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
- tmp2 = tcg_const_i32(0);
- gen_helper_neon_ceq_f32(tmp, tmp, tmp2, fpstatus);
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_ptr(fpstatus);
- break;
- }
- case NEON_2RM_VCLE0_F:
- {
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
- tmp2 = tcg_const_i32(0);
- gen_helper_neon_cge_f32(tmp, tmp2, tmp, fpstatus);
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_ptr(fpstatus);
- break;
- }
- case NEON_2RM_VCLT0_F:
- {
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
- tmp2 = tcg_const_i32(0);
- gen_helper_neon_cgt_f32(tmp, tmp2, tmp, fpstatus);
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_ptr(fpstatus);
- break;
- }
case NEON_2RM_VSWP:
tmp2 = neon_load_reg(rd, pass);
neon_store_reg(rm, pass, tmp2);
--
2.20.1
- [PATCH 11/21] target/arm: Make gen_swap_half() take separate src and dest, (continued)
- [PATCH 11/21] target/arm: Make gen_swap_half() take separate src and dest, Peter Maydell, 2020/06/16
- [PATCH 13/21] target/arm: Convert remaining simple 2-reg-misc Neon ops, Peter Maydell, 2020/06/16
- [PATCH 12/21] target/arm: Convert Neon 2-reg-misc VREV32 and VREV16 to decodetree, Peter Maydell, 2020/06/16
- [PATCH 14/21] target/arm: Convert Neon VQABS, VQNEG to decodetree, Peter Maydell, 2020/06/16
- [PATCH 15/21] target/arm: Convert simple fp Neon 2-reg-misc insns, Peter Maydell, 2020/06/16
- [PATCH 16/21] target/arm: Convert Neon 2-reg-misc fp-compare-with-zero insns to decodetree,
Peter Maydell <=
- [PATCH 17/21] target/arm: Convert Neon 2-reg-misc VRINT insns to decodetree, Peter Maydell, 2020/06/16
- [PATCH 18/21] target/arm: Convert Neon 2-reg-misc VCVT insns to decodetree, Peter Maydell, 2020/06/16
- [PATCH 19/21] target/arm: Convert Neon VSWP to decodetree, Peter Maydell, 2020/06/16
- [PATCH 21/21] target/arm: Move some functions used only in translate-neon.inc.c to that file, Peter Maydell, 2020/06/16
- [PATCH 20/21] target/arm: Convert Neon VTRN to decodetree, Peter Maydell, 2020/06/16