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[PATCH 5/8] hw/char/escc2: Add Receiver Reset (RRES) command
From: |
Jasper Lowell |
Subject: |
[PATCH 5/8] hw/char/escc2: Add Receiver Reset (RRES) command |
Date: |
Wed, 17 Jun 2020 18:23:59 +1000 |
Commands are initiated by setting certain bits in the CMDR register. The
Receiver Reset (RRES) command clears the receiver FIFO (RFIFO).
Signed-off-by: Jasper Lowell <jasper.lowell@bt.com>
---
hw/char/escc2.c | 24 ++++++++++++++++++++++++
hw/char/trace-events | 1 +
2 files changed, 25 insertions(+)
diff --git a/hw/char/escc2.c b/hw/char/escc2.c
index 059e033089..5afb8aa6d9 100644
--- a/hw/char/escc2.c
+++ b/hw/char/escc2.c
@@ -29,6 +29,12 @@
/* CMDR. */
#define REGISTER_CMDR_OFFSET 0x20
+#define REGISTER_CMDR_RMC 0x80
+#define REGISTER_CMDR_RRES 0x40
+#define REGISTER_CMDR_RFRD 0x20
+#define REGISTER_CMDR_STI 0x10
+#define REGISTER_CMDR_XF 0x8
+#define REGISTER_CMDR_XRES 0x1
/* MODE. */
#define REGISTER_MODE_OFFSET 0x22
@@ -741,6 +747,23 @@ static uint64_t escc2_mem_read(void *opaque, hwaddr addr,
unsigned size)
return value;
}
+static void escc2_channel_command(ESCC2ChannelState *channel)
+{
+ uint8_t tmp, command;
+
+ command = REGISTER_READ(channel, REGISTER_CMDR);
+ trace_escc2_channel_command(CHANNEL_CHAR(channel), command);
+
+ if (command & REGISTER_CMDR_RRES) {
+ memset(channel->fifo_receive, 0, sizeof(channel->fifo_receive));
+ REGISTER_WRITE(channel, REGISTER_RBCL, 0);
+
+ tmp = REGISTER_READ(channel, REGISTER_STAR);
+ tmp &= ~(REGISTER_STAR_RFNE);
+ REGISTER_WRITE(channel, REGISTER_STAR, tmp);
+ }
+}
+
static void escc2_mem_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
@@ -767,6 +790,7 @@ static void escc2_mem_write(void *opaque, hwaddr addr,
uint64_t value,
break;
case REGISTER_CMDR_OFFSET:
REGISTER_WRITE(channel, REGISTER_CMDR, value);
+ escc2_channel_command(channel);
break;
case REGISTER_MODE_OFFSET:
REGISTER_WRITE(channel, REGISTER_MODE, value);
diff --git a/hw/char/trace-events b/hw/char/trace-events
index b4f4f30815..47b46b92c9 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -59,6 +59,7 @@ escc_sunmouse_event(int dx, int dy, int buttons_state) "dx=%d
dy=%d buttons=0x%0
# escc2.c
escc2_irq_update(uint8_t gis) "value 0x%x"
escc2_mem_read(char channel, uint32_t addr, uint8_t value) "channel %c addr
0x%x value 0x%x"
+escc2_channel_command(char channel, uint8_t command) "channel %c command 0x%x"
escc2_mem_write(char channel, uint32_t addr, uint8_t value) "channel %c addr
0x%x value 0x%x"
# pl011.c
--
2.26.2
- [PATCH 0/8] ESCC2, Jasper Lowell, 2020/06/17
- [PATCH 1/8] hw/char/escc2: Add device, Jasper Lowell, 2020/06/17
- [PATCH 2/8] hw/char/escc2: Handle interrupt generation, Jasper Lowell, 2020/06/17
- [PATCH 3/8] hw/char/escc2: Add character device backend, Jasper Lowell, 2020/06/17
- [PATCH 5/8] hw/char/escc2: Add Receiver Reset (RRES) command,
Jasper Lowell <=
- [PATCH 4/8] hw/char/escc2: Add clock generation, Jasper Lowell, 2020/06/17
- [PATCH 6/8] hw/char/escc2: Add RFRD command, Jasper Lowell, 2020/06/17
- [PATCH 7/8] hw/char/escc2: Add Transmit Frame (XF) command, Jasper Lowell, 2020/06/17
- [PATCH 8/8] hw/char/escc2: Add XRES command, Jasper Lowell, 2020/06/17
- Re: [PATCH 0/8] ESCC2, no-reply, 2020/06/17
- Re: [PATCH 0/8] ESCC2, Philippe Mathieu-Daudé, 2020/06/17
- Re: [PATCH 0/8] ESCC2, Artyom Tarasenko, 2020/06/17