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[PATCH v2 1/7] target/ppc: Introduce Power ISA 3.1 flag
From: |
Lijun Pan |
Subject: |
[PATCH v2 1/7] target/ppc: Introduce Power ISA 3.1 flag |
Date: |
Wed, 17 Jun 2020 19:11:21 -0500 |
This flag will be used for Power10 instructions.
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v2: add Power ISA 3.1 flag
target/ppc/cpu.h | 4 +++-
target/ppc/translate_init.inc.c | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 1988b436cb..ebb5a0811a 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2191,6 +2191,8 @@ enum {
PPC2_PM_ISA206 = 0x0000000000040000ULL,
/* POWER ISA 3.0 */
PPC2_ISA300 = 0x0000000000080000ULL,
+ /* POWER ISA 3.1 */
+ PPC2_ISA310 = 0x0000000000100000ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
@@ -2199,7 +2201,7 @@ enum {
PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
- PPC2_ISA300)
+ PPC2_ISA300 | PPC2_ISA310)
};
/*****************************************************************************/
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 38cb773ab4..3f72310e60 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -9206,7 +9206,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
- PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
+ PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_HV) |
(1ull << MSR_TM) |
--
2.23.0
- [PATCH v2 0/7] Add several Power ISA 3.1 32/64-bit vector instructions, Lijun Pan, 2020/06/17
- [PATCH v2 3/7] target/ppc: add vmulld instruction, Lijun Pan, 2020/06/17
- [PATCH v2 2/7] target/ppc: add byte-reverse br[dwh] instructions, Lijun Pan, 2020/06/17
- [PATCH v2 1/7] target/ppc: Introduce Power ISA 3.1 flag,
Lijun Pan <=
- [PATCH v2 5/7] fix the prototype of muls64/mulu64, Lijun Pan, 2020/06/17
- [PATCH v2 7/7] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions, Lijun Pan, 2020/06/17
- [PATCH v2 6/7] target/ppc: add vmulh{su}d instructions, Lijun Pan, 2020/06/17
- [PATCH v2 4/7] target/ppc: add vmulh{su}w instructions, Lijun Pan, 2020/06/17
- Re: [PATCH v2 0/7] Add several Power ISA 3.1 32/64-bit vector instructions, no-reply, 2020/06/17