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[PULL 10/32] target/riscv: Implement checks for hfence
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From: |
Alistair Francis |
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Subject: |
[PULL 10/32] target/riscv: Implement checks for hfence |
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Date: |
Thu, 18 Jun 2020 23:24:56 -0700 |
Call the helper_hyp_tlb_flush() function on hfence instructions which
will generate an illegal insruction execption if we don't have
permission to flush the Hypervisor level TLBs.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 5 ++++
target/riscv/insn_trans/trans_rvh.inc.c | 32 +++++--------------------
target/riscv/op_helper.c | 13 ++++++++++
3 files changed, 24 insertions(+), 26 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index debb22a480..b36be978d5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -76,3 +76,8 @@ DEF_HELPER_2(mret, tl, env, tl)
DEF_HELPER_1(wfi, void, env)
DEF_HELPER_1(tlb_flush, void, env)
#endif
+
+/* Hypervisor functions */
+#ifndef CONFIG_USER_ONLY
+DEF_HELPER_1(hyp_tlb_flush, void, env)
+#endif
diff --git a/target/riscv/insn_trans/trans_rvh.inc.c
b/target/riscv/insn_trans/trans_rvh.inc.c
index 2c0359819d..263b652d90 100644
--- a/target/riscv/insn_trans/trans_rvh.inc.c
+++ b/target/riscv/insn_trans/trans_rvh.inc.c
@@ -18,40 +18,20 @@
static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
{
+ REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY
- if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
- has_ext(ctx, RVH)) {
- /* Hpervisor extensions exist */
- /*
- * if (env->priv == PRV_M ||
- * (env->priv == PRV_S &&
- * !riscv_cpu_virt_enabled(env) &&
- * get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
- */
- gen_helper_tlb_flush(cpu_env);
- return true;
- /* } */
- }
+ gen_helper_hyp_tlb_flush(cpu_env);
+ return true;
#endif
return false;
}
static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a)
{
+ REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY
- if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
- has_ext(ctx, RVH)) {
- /* Hpervisor extensions exist */
- /*
- * if (env->priv == PRV_M ||
- * (env->priv == PRV_S &&
- * !riscv_cpu_virt_enabled(env) &&
- * get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
- */
- gen_helper_tlb_flush(cpu_env);
- return true;
- /* } */
- }
+ gen_helper_hyp_tlb_flush(cpu_env);
+ return true;
#endif
return false;
}
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index b0c49efc4a..7cccd42a1e 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -194,4 +194,17 @@ void helper_tlb_flush(CPURISCVState *env)
}
}
+void helper_hyp_tlb_flush(CPURISCVState *env)
+{
+ CPUState *cs = env_cpu(env);
+
+ if (env->priv == PRV_M ||
+ (env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) {
+ tlb_flush(cs);
+ return;
+ }
+
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+}
+
#endif /* !CONFIG_USER_ONLY */
--
2.27.0
- [PULL 15/32] riscv/opentitan: Connect the UART device, (continued)
- [PULL 15/32] riscv/opentitan: Connect the UART device, Alistair Francis, 2020/06/19
- [PULL 02/32] sifive_e: Support the revB machine, Alistair Francis, 2020/06/19
- [PULL 04/32] riscv: Generalize CPU init routine for the gcsu CPU, Alistair Francis, 2020/06/19
- [PULL 18/32] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions, Alistair Francis, 2020/06/19
- [PULL 16/32] target/riscv: Use a smaller guess size for no-MMU PMP, Alistair Francis, 2020/06/19
- [PULL 14/32] riscv/opentitan: Connect the PLIC device, Alistair Francis, 2020/06/19
- [PULL 06/32] riscv: Keep the CPU init routine names consistent, Alistair Francis, 2020/06/19
- [PULL 21/32] hw/riscv: sifive_gpio: Clean up the codes, Alistair Francis, 2020/06/19
- [PULL 07/32] target/riscv: Set access as data_load when validating stage-2 PTEs, Alistair Francis, 2020/06/19
- [PULL 01/32] riscv: Add helper to make NaN-boxing for FP register, Alistair Francis, 2020/06/19
- [PULL 10/32] target/riscv: Implement checks for hfence,
Alistair Francis <=
- [PULL 11/32] riscv/opentitan: Fix the ROM size, Alistair Francis, 2020/06/19
- [PULL 03/32] riscv: Generalize CPU init routine for the base CPU, Alistair Francis, 2020/06/19
- [PULL 13/32] hw/intc: Initial commit of lowRISC Ibex PLIC, Alistair Francis, 2020/06/19
- [PULL 17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions, Alistair Francis, 2020/06/19
- [PULL 05/32] riscv: Generalize CPU init routine for the imacu CPU, Alistair Francis, 2020/06/19
- [PULL 19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit, Alistair Francis, 2020/06/19
- [PULL 08/32] target/riscv: Report errors validating 2nd-stage PTEs, Alistair Francis, 2020/06/19
- [PULL 20/32] hw/riscv: sifive_u: Generate device tree node for OTP, Alistair Francis, 2020/06/19
- [PULL 22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property, Alistair Francis, 2020/06/19
- [PULL 09/32] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/06/19