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Re: [PULL v2 00/32] riscv-to-apply queue
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From: |
Peter Maydell |
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Subject: |
Re: [PULL v2 00/32] riscv-to-apply queue |
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Date: |
Mon, 22 Jun 2020 16:01:27 +0100 |
On Fri, 19 Jun 2020 at 18:07, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 4d285821c5055ed68a6f6b7693fd11a06a1aa426:
>
> Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200618' into
> staging (2020-06-19 11:44:03 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200619-3
>
> for you to fetch changes up to 3eaea6eb4e534f7b87c6eca808149bb671976800:
>
> hw/riscv: sifive_u: Add a dummy DDR memory controller device (2020-06-19
> 08:25:27 -0700)
>
> ----------------------------------------------------------------
> This is a range of patches for RISC-V.
>
> Some key points are:
> - Generalise the CPU init functions
> - Support the SiFive revB machine
> - Improvements to the Hypervisor implementation and error checking
> - Connect some OpenTitan devices
> - Changes to the sifive_u machine to support U-boot
>
> v2:
> - Fix missing realise assert
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1
for any user-visible changes.
-- PMM
- [PULL v2 25/32] hw/riscv: sifive_u: Add reset functionality, (continued)
- [PULL v2 25/32] hw/riscv: sifive_u: Add reset functionality, Alistair Francis, 2020/06/19
- [PULL v2 26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name, Alistair Francis, 2020/06/19
- [PULL v2 27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state, Alistair Francis, 2020/06/19
- [PULL v2 13/32] hw/intc: Initial commit of lowRISC Ibex PLIC, Alistair Francis, 2020/06/19
- [PULL v2 28/32] target/riscv: Rename IBEX CPU init routine, Alistair Francis, 2020/06/19
- [PULL v2 29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004, Alistair Francis, 2020/06/19
- [PULL v2 30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state, Alistair Francis, 2020/06/19
- [PULL v2 31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries, Alistair Francis, 2020/06/19
- [PULL v2 32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device, Alistair Francis, 2020/06/19
- Re: [PULL v2 00/32] riscv-to-apply queue, no-reply, 2020/06/19
- Re: [PULL v2 00/32] riscv-to-apply queue,
Peter Maydell <=