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[PULL 13/42] target/arm: Make gen_swap_half() take separate src and dest
From: |
Peter Maydell |
Subject: |
[PULL 13/42] target/arm: Make gen_swap_half() take separate src and dest |
Date: |
Tue, 23 Jun 2020 12:38:35 +0100 |
Make gen_swap_half() take a source and destination TCGv_i32 rather
than modifying the input TCGv_i32; we're going to want to be able to
use it with the more flexible function signature, and this also
brings it into line with other functions like gen_rev16() and
gen_revsh().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-12-peter.maydell@linaro.org
---
target/arm/translate-neon.inc.c | 2 +-
target/arm/translate.c | 10 +++++-----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index c39443c8cae..4967e974386 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -3007,7 +3007,7 @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
tcg_gen_bswap32_i32(tmp[half], tmp[half]);
break;
case 1:
- gen_swap_half(tmp[half]);
+ gen_swap_half(tmp[half], tmp[half]);
break;
case 2:
break;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 38644995ab2..64b18a95b64 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -378,9 +378,9 @@ static void gen_revsh(TCGv_i32 dest, TCGv_i32 var)
}
/* Swap low and high halfwords. */
-static void gen_swap_half(TCGv_i32 var)
+static void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
{
- tcg_gen_rotri_i32(var, var, 16);
+ tcg_gen_rotri_i32(dest, var, 16);
}
/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
@@ -4960,7 +4960,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t
insn)
case NEON_2RM_VREV32:
switch (size) {
case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
- case 1: gen_swap_half(tmp); break;
+ case 1: gen_swap_half(tmp, tmp); break;
default: abort();
}
break;
@@ -8046,7 +8046,7 @@ static bool op_smlad(DisasContext *s, arg_rrrr *a, bool
m_swap, bool sub)
t1 = load_reg(s, a->rn);
t2 = load_reg(s, a->rm);
if (m_swap) {
- gen_swap_half(t2);
+ gen_swap_half(t2, t2);
}
gen_smul_dual(t1, t2);
@@ -8104,7 +8104,7 @@ static bool op_smlald(DisasContext *s, arg_rrrr *a, bool
m_swap, bool sub)
t1 = load_reg(s, a->rn);
t2 = load_reg(s, a->rm);
if (m_swap) {
- gen_swap_half(t2);
+ gen_swap_half(t2, t2);
}
gen_smul_dual(t1, t2);
--
2.20.1
- [PULL 02/42] util/oslib-posix : qemu_init_exec_dir implementation for Mac, (continued)
- [PULL 02/42] util/oslib-posix : qemu_init_exec_dir implementation for Mac, Peter Maydell, 2020/06/23
- [PULL 03/42] target/arm: Convert Neon 2-reg-misc VREV64 to decodetree, Peter Maydell, 2020/06/23
- [PULL 05/42] target/arm: Convert VZIP, VUZP to decodetree, Peter Maydell, 2020/06/23
- [PULL 04/42] target/arm: Convert Neon 2-reg-misc pairwise ops to decodetree, Peter Maydell, 2020/06/23
- [PULL 07/42] target/arm: Convert Neon 2-reg-misc VSHLL to decodetree, Peter Maydell, 2020/06/23
- [PULL 06/42] target/arm: Convert Neon narrowing moves to decodetree, Peter Maydell, 2020/06/23
- [PULL 08/42] target/arm: Convert Neon VCVT f16/f32 insns to decodetree, Peter Maydell, 2020/06/23
- [PULL 09/42] target/arm: Convert vectorised 2-reg-misc Neon ops to decodetree, Peter Maydell, 2020/06/23
- [PULL 11/42] target/arm: Rename NeonGenOneOpFn to NeonGenOne64OpFn, Peter Maydell, 2020/06/23
- [PULL 10/42] target/arm: Convert Neon 2-reg-misc crypto operations to decodetree, Peter Maydell, 2020/06/23
- [PULL 13/42] target/arm: Make gen_swap_half() take separate src and dest,
Peter Maydell <=
- [PULL 14/42] target/arm: Convert Neon 2-reg-misc VREV32 and VREV16 to decodetree, Peter Maydell, 2020/06/23
- [PULL 12/42] target/arm: Fix capitalization in NeonGenTwo{Single, Double}OPFn typedefs, Peter Maydell, 2020/06/23
- [PULL 15/42] target/arm: Convert remaining simple 2-reg-misc Neon ops, Peter Maydell, 2020/06/23
- [PULL 16/42] target/arm: Convert Neon VQABS, VQNEG to decodetree, Peter Maydell, 2020/06/23
- [PULL 17/42] target/arm: Convert simple fp Neon 2-reg-misc insns, Peter Maydell, 2020/06/23
- [PULL 18/42] target/arm: Convert Neon 2-reg-misc fp-compare-with-zero insns to decodetree, Peter Maydell, 2020/06/23
- [PULL 19/42] target/arm: Convert Neon 2-reg-misc VRINT insns to decodetree, Peter Maydell, 2020/06/23
- [PULL 20/42] target/arm: Convert Neon 2-reg-misc VCVT insns to decodetree, Peter Maydell, 2020/06/23
- [PULL 21/42] target/arm: Convert Neon VSWP to decodetree, Peter Maydell, 2020/06/23
- [PULL 23/42] target/arm: Move some functions used only in translate-neon.inc.c to that file, Peter Maydell, 2020/06/23