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[PATCH v8 38/45] target/arm: Complete TBI clearing for user-only for SVE
From: |
Richard Henderson |
Subject: |
[PATCH v8 38/45] target/arm: Complete TBI clearing for user-only for SVE |
Date: |
Tue, 23 Jun 2020 12:36:51 -0700 |
There are a number of paths by which the TBI is still intact
for user-only in the SVE helpers.
Because we currently always set TBI for user-only, we do not
need to pass down the actual TBI setting from above, and we
can remove the top byte in the inner-most primitives, so that
none are forgotten. Moreover, this keeps the "dirty" pointer
around at the higher levels, where we need it for any MTE checking.
Since the normal case, especially for user-only, goes through
RAM, this clearing merely adds two insns per page lookup, which
will be completely in the noise.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sve_helper.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index ad974c2cc5..382fa82bc8 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -3966,14 +3966,16 @@ static void sve_##NAME##_host(void *vd, intptr_t
reg_off, void *host) \
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
target_ulong addr, uintptr_t ra) \
{ \
- *(TYPEE *)(vd + H(reg_off)) = (TYPEM)TLB(env, addr, ra); \
+ *(TYPEE *)(vd + H(reg_off)) = \
+ (TYPEM)TLB(env, useronly_clean_ptr(addr), ra); \
}
#define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
target_ulong addr, uintptr_t ra) \
{ \
- TLB(env, addr, (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); \
+ TLB(env, useronly_clean_ptr(addr), \
+ (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); \
}
#define DO_LD_PRIM_1(NAME, H, TE, TM) \
@@ -4091,6 +4093,19 @@ static bool sve_probe_page(SVEHostPage *info, bool
nofault,
int flags;
addr += mem_off;
+
+ /*
+ * User-only currently always issues with TBI. See the comment
+ * above useronly_clean_ptr. Usually we clean this top byte away
+ * during translation, but we can't do that for e.g. vector + imm
+ * addressing modes.
+ *
+ * We currently always enable TBI for user-only, and do not provide
+ * a way to turn it off. So clean the pointer unconditionally here,
+ * rather than look it up here, or pass it down from above.
+ */
+ addr = useronly_clean_ptr(addr);
+
flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault,
&info->host, retaddr);
info->flags = flags;
--
2.25.1
- [PATCH v8 32/45] target/arm: Add arm_tlb_bti_gp, (continued)
- [PATCH v8 32/45] target/arm: Add arm_tlb_bti_gp, Richard Henderson, 2020/06/23
- [PATCH v8 34/45] target/arm: Add mte helpers for sve scalar + int stores, Richard Henderson, 2020/06/23
- [PATCH v8 36/45] target/arm: Handle TBI for sve scalar + int memory ops, Richard Henderson, 2020/06/23
- [PATCH v8 33/45] target/arm: Add mte helpers for sve scalar + int loads, Richard Henderson, 2020/06/23
- [PATCH v8 35/45] target/arm: Add mte helpers for sve scalar + int ff/nf loads, Richard Henderson, 2020/06/23
- [PATCH v8 38/45] target/arm: Complete TBI clearing for user-only for SVE,
Richard Henderson <=
- [PATCH v8 40/45] target/arm: Set PSTATE.TCO on exception entry, Richard Henderson, 2020/06/23
- [PATCH v8 39/45] target/arm: Implement data cache set allocation tags, Richard Henderson, 2020/06/23
- [PATCH v8 37/45] target/arm: Add mte helpers for sve scatter/gather memory ops, Richard Henderson, 2020/06/23
- [PATCH v8 42/45] target/arm: Cache the Tagged bit for a page in MemTxAttrs, Richard Henderson, 2020/06/23
- [PATCH v8 41/45] target/arm: Always pass cacheattr to get_phys_addr, Richard Henderson, 2020/06/23