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[PATCH v9 02/46] target/arm: Improve masking of SCR RES0 bits
From: |
Richard Henderson |
Subject: |
[PATCH v9 02/46] target/arm: Improve masking of SCR RES0 bits |
Date: |
Thu, 25 Jun 2020 20:31:00 -0700 |
Protect reads of aa64 id registers with ARM_CP_STATE_AA64.
Use this as a simpler test than arm_el_is_aa64, since EL3
cannot change mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 972a766730..a29f0a28d8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2011,9 +2011,16 @@ static void scr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
uint32_t valid_mask = 0x3fff;
ARMCPU *cpu = env_archcpu(env);
- if (arm_el_is_aa64(env, 3)) {
+ if (ri->state == ARM_CP_STATE_AA64) {
value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
valid_mask &= ~SCR_NET;
+
+ if (cpu_isar_feature(aa64_lor, cpu)) {
+ valid_mask |= SCR_TLOR;
+ }
+ if (cpu_isar_feature(aa64_pauth, cpu)) {
+ valid_mask |= SCR_API | SCR_APK;
+ }
} else {
valid_mask &= ~(SCR_RW | SCR_ST);
}
@@ -2032,12 +2039,6 @@ static void scr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
valid_mask &= ~SCR_SMD;
}
}
- if (cpu_isar_feature(aa64_lor, cpu)) {
- valid_mask |= SCR_TLOR;
- }
- if (cpu_isar_feature(aa64_pauth, cpu)) {
- valid_mask |= SCR_API | SCR_APK;
- }
/* Clear all-context RES0 bits. */
value &= valid_mask;
--
2.25.1
- [PATCH v9 00/46] target/arm: Implement ARMv8.5-MemTag, system mode, Richard Henderson, 2020/06/25
- [PATCH v9 01/46] target/arm: Add isar tests for mte, Richard Henderson, 2020/06/25
- [PATCH v9 02/46] target/arm: Improve masking of SCR RES0 bits,
Richard Henderson <=
- [PATCH v9 03/46] target/arm: Add support for MTE to SCTLR_ELx, Richard Henderson, 2020/06/25
- [PATCH v9 04/46] target/arm: Add support for MTE to HCR_EL2 and SCR_EL3, Richard Henderson, 2020/06/25
- [PATCH v9 05/46] target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT, Richard Henderson, 2020/06/25
- [PATCH v9 06/46] target/arm: Add DISAS_UPDATE_NOCHAIN, Richard Henderson, 2020/06/25
- [PATCH v9 07/46] target/arm: Add MTE system registers, Richard Henderson, 2020/06/25
- [PATCH v9 08/46] target/arm: Add MTE bits to tb_flags, Richard Henderson, 2020/06/25
- [PATCH v9 09/46] target/arm: Implement the IRG instruction, Richard Henderson, 2020/06/25
- [PATCH v9 10/46] target/arm: Revise decoding for disas_add_sub_imm, Richard Henderson, 2020/06/25
- [PATCH v9 11/46] target/arm: Implement the ADDG, SUBG instructions, Richard Henderson, 2020/06/25
- [PATCH v9 12/46] target/arm: Implement the GMI instruction, Richard Henderson, 2020/06/25