Re: [PATCH v9 00/46] target/arm: Implement ARMv8.5-MemTag, system mode

[no-reply]

Patchew URL: 
20200626033144.790098-1-richard.henderson@linaro.org/">https://patchew.org/QEMU/20200626033144.790098-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PATCH v9 00/46] target/arm: Implement ARMv8.5-MemTag, system mode
Type: series
Message-id: 20200626033144.790098-1-richard.henderson@linaro.org

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
 - [tag update]      
patchew/20200626033144.790098-1-richard.henderson@linaro.org -> 
patchew/20200626033144.790098-1-richard.henderson@linaro.org
Switched to a new branch 'test'
f9c5338 target/arm: Add arm,armv8.5-memtag to dtb
50373ce target/arm: Enable MTE
5e43981 target/arm: Add allocation tag storage for system mode
b716019 target/arm: Create tagged ram when MTE is enabled
54dffdd target/arm: Cache the Tagged bit for a page in MemTxAttrs
e9d7c0c target/arm: Always pass cacheattr to get_phys_addr
5b4bb08 target/arm: Set PSTATE.TCO on exception entry
2374105 target/arm: Implement data cache set allocation tags
d00eb58 target/arm: Complete TBI clearing for user-only for SVE
a259ae4 target/arm: Add mte helpers for sve scatter/gather memory ops
a42b648 target/arm: Handle TBI for sve scalar + int memory ops
4b412c5 target/arm: Add mte helpers for sve scalar + int ff/nf loads
e0186f9 target/arm: Add mte helpers for sve scalar + int stores
c576e49 target/arm: Add mte helpers for sve scalar + int loads
ed24264 target/arm: Add arm_tlb_bti_gp
ff4e523 target/arm: Tidy trans_LD1R_zpri
44daf9e target/arm: Use mte_check1 for sve LD1R
4c9e8db target/arm: Use mte_checkN for sve unpredicated stores
d44ff24 target/arm: Use mte_checkN for sve unpredicated loads
f998d46 target/arm: Add helper_mte_check_zva
717954f target/arm: Implement helper_mte_checkN
65173b3 target/arm: Implement helper_mte_check1
c3c6b6e target/arm: Add gen_mte_checkN
4c7848f target/arm: Add gen_mte_check1
f2a85d3 target/arm: Move regime_tcr to internals.h
28cc6ee target/arm: Move regime_el to internals.h
2f468a1 target/arm: Implement the access tag cache flushes
fbdcf28 target/arm: Implement the LDGM, STGM, STZGM instructions
af47c61 target/arm: Simplify DC_ZVA
2462cc0 target/arm: Restrict the values of DCZID.BS under TCG
10f3a95 target/arm: Implement the STGP instruction
cf161ed target/arm: Implement LDG, STG, ST2G instructions
a871478 target/arm: Define arm_cpu_do_unaligned_access for user-only
e5e68d2 target/arm: Implement the SUBP instruction
59e4015 target/arm: Implement the GMI instruction
41e37a6 target/arm: Implement the ADDG, SUBG instructions
e16dacf target/arm: Revise decoding for disas_add_sub_imm
30e907e target/arm: Implement the IRG instruction
88bf5ec target/arm: Add MTE bits to tb_flags
42a90e2 target/arm: Add MTE system registers
4eebaf9 target/arm: Add DISAS_UPDATE_NOCHAIN
3803a5a target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT
6dcc087 target/arm: Add support for MTE to HCR_EL2 and SCR_EL3
1ffbabf target/arm: Add support for MTE to SCTLR_ELx
f5db6d8 target/arm: Improve masking of SCR RES0 bits
0529812 target/arm: Add isar tests for mte

=== OUTPUT BEGIN ===
1/46 Checking commit 0529812ba00c (target/arm: Add isar tests for mte)
2/46 Checking commit f5db6d8b0561 (target/arm: Improve masking of SCR RES0 bits)
3/46 Checking commit 1ffbabf944e2 (target/arm: Add support for MTE to SCTLR_ELx)
4/46 Checking commit 6dcc0876172b (target/arm: Add support for MTE to HCR_EL2 
and SCR_EL3)
5/46 Checking commit 3803a5a8f556 (target/arm: Rename DISAS_UPDATE to 
DISAS_UPDATE_EXIT)
6/46 Checking commit 4eebaf929f15 (target/arm: Add DISAS_UPDATE_NOCHAIN)
7/46 Checking commit 42a90e2dc7a7 (target/arm: Add MTE system registers)
8/46 Checking commit 88bf5ec2264c (target/arm: Add MTE bits to tb_flags)
9/46 Checking commit 30e907e6cbd7 (target/arm: Implement the IRG instruction)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#45: 
new file mode 100644

total: 0 errors, 1 warnings, 120 lines checked

Patch 9/46 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/46 Checking commit e16dacf7de7d (target/arm: Revise decoding for 
disas_add_sub_imm)
11/46 Checking commit 41e37a609ce0 (target/arm: Implement the ADDG, SUBG 
instructions)
12/46 Checking commit 59e4015f372a (target/arm: Implement the GMI instruction)
13/46 Checking commit e5e68d267788 (target/arm: Implement the SUBP instruction)
14/46 Checking commit a87147851d90 (target/arm: Define 
arm_cpu_do_unaligned_access for user-only)
15/46 Checking commit cf161ed3a7e1 (target/arm: Implement LDG, STG, ST2G 
instructions)
16/46 Checking commit 10f3a9533353 (target/arm: Implement the STGP instruction)
17/46 Checking commit 2462cc02a351 (target/arm: Restrict the values of DCZID.BS 
under TCG)
18/46 Checking commit af47c6154ba2 (target/arm: Simplify DC_ZVA)
19/46 Checking commit fbdcf28bd7c3 (target/arm: Implement the LDGM, STGM, STZGM 
instructions)
20/46 Checking commit 2f468a147ad2 (target/arm: Implement the access tag cache 
flushes)
21/46 Checking commit 28cc6ee1e400 (target/arm: Move regime_el to internals.h)
22/46 Checking commit f2a85d318b32 (target/arm: Move regime_tcr to internals.h)
23/46 Checking commit 4c7848f867be (target/arm: Add gen_mte_check1)
24/46 Checking commit c3c6b6e91fe8 (target/arm: Add gen_mte_checkN)
25/46 Checking commit 65173b3f2b54 (target/arm: Implement helper_mte_check1)
26/46 Checking commit 717954fa82cc (target/arm: Implement helper_mte_checkN)
27/46 Checking commit f998d46b2bc4 (target/arm: Add helper_mte_check_zva)
28/46 Checking commit d44ff244144d (target/arm: Use mte_checkN for sve 
unpredicated loads)
29/46 Checking commit 4c9e8dbb0f8d (target/arm: Use mte_checkN for sve 
unpredicated stores)
30/46 Checking commit 44daf9e92a49 (target/arm: Use mte_check1 for sve LD1R)
31/46 Checking commit ff4e5239a817 (target/arm: Tidy trans_LD1R_zpri)
32/46 Checking commit ed242645700b (target/arm: Add arm_tlb_bti_gp)
33/46 Checking commit c576e49abee0 (target/arm: Add mte helpers for sve scalar 
+ int loads)
34/46 Checking commit e0186f9efd46 (target/arm: Add mte helpers for sve scalar 
+ int stores)
35/46 Checking commit 4b412c552991 (target/arm: Add mte helpers for sve scalar 
+ int ff/nf loads)
36/46 Checking commit a42b648c561e (target/arm: Handle TBI for sve scalar + int 
memory ops)
37/46 Checking commit a259ae491cee (target/arm: Add mte helpers for sve 
scatter/gather memory ops)
38/46 Checking commit d00eb58f4686 (target/arm: Complete TBI clearing for 
user-only for SVE)
ERROR: spaces required around that '*' (ctx:VxV)
#57: FILE: target/arm/sve_helper.c:3978:
+        (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra);                            \
                ^

total: 1 errors, 0 warnings, 57 lines checked

Patch 38/46 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

39/46 Checking commit 2374105a46e8 (target/arm: Implement data cache set 
allocation tags)
40/46 Checking commit 5b4bb0856135 (target/arm: Set PSTATE.TCO on exception 
entry)
41/46 Checking commit e9d7c0ce20a8 (target/arm: Always pass cacheattr to 
get_phys_addr)
42/46 Checking commit 54dffddc5b17 (target/arm: Cache the Tagged bit for a page 
in MemTxAttrs)
43/46 Checking commit b716019a48f9 (target/arm: Create tagged ram when MTE is 
enabled)
44/46 Checking commit 5e43981e3d60 (target/arm: Add allocation tag storage for 
system mode)
45/46 Checking commit 50373ce98b3a (target/arm: Enable MTE)
46/46 Checking commit f9c53383ab18 (target/arm: Add arm,armv8.5-memtag to dtb)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
20200626033144.790098-1-richard.henderson@linaro.org/testing.checkpatch/?type=message">http://patchew.org/logs/20200626033144.790098-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
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