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[PULL 04/63] target/riscv: implementation-defined constant parameters
From: |
Alistair Francis |
Subject: |
[PULL 04/63] target/riscv: implementation-defined constant parameters |
Date: |
Fri, 26 Jun 2020 14:43:11 -0700 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200623215920.2594-3-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 5 +++++
target/riscv/cpu.c | 7 +++++++
2 files changed, 12 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0018a79fa3..302e0859a0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -78,6 +78,8 @@ enum {
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
+#define VEXT_VERSION_0_07_1 0x00000701
+
#define TRANSLATE_PMP_FAIL 2
#define TRANSLATE_FAIL 1
#define TRANSLATE_SUCCESS 0
@@ -113,6 +115,7 @@ struct CPURISCVState {
target_ulong guest_phys_fault_addr;
target_ulong priv_ver;
+ target_ulong vext_ver;
target_ulong misa;
target_ulong misa_mask;
@@ -275,6 +278,8 @@ typedef struct RISCVCPU {
char *priv_spec;
char *user_spec;
+ uint16_t vlen;
+ uint16_t elen;
bool mmu;
bool pmp;
} cfg;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 391a0b9eec..d525cfb687 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -106,6 +106,11 @@ static void set_priv_version(CPURISCVState *env, int
priv_ver)
env->priv_ver = priv_ver;
}
+static void set_vext_version(CPURISCVState *env, int vext_ver)
+{
+ env->vext_ver = vext_ver;
+}
+
static void set_feature(CPURISCVState *env, int feature)
{
env->features |= (1ULL << feature);
@@ -334,6 +339,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
int priv_version = PRIV_VERSION_1_11_0;
+ int vext_version = VEXT_VERSION_0_07_1;
target_ulong target_misa = 0;
Error *local_err = NULL;
@@ -357,6 +363,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
set_priv_version(env, priv_version);
+ set_vext_version(env, vext_version);
if (cpu->cfg.mmu) {
set_feature(env, RISCV_FEATURE_MMU);
--
2.27.0
- [PULL 00/63] riscv-to-apply queue, Alistair Francis, 2020/06/26
- [PULL 11/63] target/riscv: add vector amo operations, Alistair Francis, 2020/06/26
- [PULL 12/63] target/riscv: vector single-width integer add and subtract, Alistair Francis, 2020/06/26
- [PULL 13/63] target/riscv: vector widening integer add and subtract, Alistair Francis, 2020/06/26
- [PULL 01/63] riscv: plic: Honour source priorities, Alistair Francis, 2020/06/26
- [PULL 02/63] riscv: plic: Add a couple of mising sifive_plic_update calls, Alistair Francis, 2020/06/26
- [PULL 04/63] target/riscv: implementation-defined constant parameters,
Alistair Francis <=
- [PULL 15/63] target/riscv: vector bitwise logical instructions, Alistair Francis, 2020/06/26
- [PULL 05/63] target/riscv: support vector extension csr, Alistair Francis, 2020/06/26
- [PULL 16/63] target/riscv: vector single-width bit shift instructions, Alistair Francis, 2020/06/26
- [PULL 14/63] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions, Alistair Francis, 2020/06/26
- [PULL 03/63] target/riscv: add vector extension field in CPURISCVState, Alistair Francis, 2020/06/26
- [PULL 19/63] target/riscv: vector integer min/max instructions, Alistair Francis, 2020/06/26
- [PULL 35/63] target/riscv: vector widening floating-point multiply, Alistair Francis, 2020/06/26
- [PULL 06/63] target/riscv: add vector configure instruction, Alistair Francis, 2020/06/26
- [PULL 07/63] target/riscv: add an internals.h header, Alistair Francis, 2020/06/26
- [PULL 17/63] target/riscv: vector narrowing integer right shift instructions, Alistair Francis, 2020/06/26