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[PULL 43/63] target/riscv: vector floating-point merge instructions
From: |
Alistair Francis |
Subject: |
[PULL 43/63] target/riscv: vector floating-point merge instructions |
Date: |
Fri, 26 Jun 2020 14:43:50 -0700 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200623215920.2594-42-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 38 +++++++++++++++++++++++++
target/riscv/vector_helper.c | 24 ++++++++++++++++
4 files changed, 68 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index fb744c5ec9..2c3f0a4e0c 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1000,3 +1000,7 @@ DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env,
i32)
DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vfmerge_vfm_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfmerge_vfm_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfmerge_vfm_d, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6912eda259..38e7445a16 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -515,6 +515,8 @@ vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm
+vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
+vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 361bdce654..b6872376ce 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2184,3 +2184,41 @@ GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
/* Vector Floating-Point Classify Instruction */
GEN_OPFV_TRANS(vfclass_v, opfv_check)
+
+/* Vector Floating-Point Merge Instruction */
+GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check)
+
+static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
+{
+ if (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rd, false) &&
+ (s->sew != 0)) {
+
+ if (s->vl_eq_vlmax) {
+ tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
+ } else {
+ TCGv_ptr dest;
+ TCGv_i32 desc;
+ uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ static gen_helper_vmv_vx * const fns[3] = {
+ gen_helper_vmv_v_x_h,
+ gen_helper_vmv_v_x_w,
+ gen_helper_vmv_v_x_d,
+ };
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ dest = tcg_temp_new_ptr();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
+ fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_i32(desc);
+ gen_set_label(over);
+ }
+ return true;
+ }
+ return false;
+}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 67cd409112..51c86a5acf 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4194,3 +4194,27 @@ RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d)
GEN_VEXT_V(vfclass_v_h, 2, 2, clearh)
GEN_VEXT_V(vfclass_v_w, 4, 4, clearl)
GEN_VEXT_V(vfclass_v_d, 8, 8, clearq)
+
+/* Vector Floating-Point Merge Instruction */
+#define GEN_VFMERGE_VF(NAME, ETYPE, H, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t mlen = vext_mlen(desc); \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
+ *((ETYPE *)vd + H(i)) \
+ = (!vm && !vext_elem_mask(v0, mlen, i) ? s2 : s1); \
+ } \
+ CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+}
+
+GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2, clearh)
+GEN_VFMERGE_VF(vfmerge_vfm_w, int32_t, H4, clearl)
+GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8, clearq)
--
2.27.0
- [PULL 42/63] target/riscv: vector floating-point classify instructions, (continued)
- [PULL 42/63] target/riscv: vector floating-point classify instructions, Alistair Francis, 2020/06/26
- [PULL 08/63] target/riscv: add vector stride load and store instructions, Alistair Francis, 2020/06/26
- [PULL 39/63] target/riscv: vector floating-point min/max instructions, Alistair Francis, 2020/06/26
- [PULL 38/63] target/riscv: vector floating-point square-root instruction, Alistair Francis, 2020/06/26
- [PULL 40/63] target/riscv: vector floating-point sign-injection instructions, Alistair Francis, 2020/06/26
- [PULL 28/63] target/riscv: vector single-width fractional multiply with rounding and saturation, Alistair Francis, 2020/06/26
- [PULL 22/63] target/riscv: vector widening integer multiply instructions, Alistair Francis, 2020/06/26
- [PULL 23/63] target/riscv: vector single-width integer multiply-add instructions, Alistair Francis, 2020/06/26
- [PULL 09/63] target/riscv: add vector index load and store instructions, Alistair Francis, 2020/06/26
- [PULL 41/63] target/riscv: vector floating-point compare instructions, Alistair Francis, 2020/06/26
- [PULL 43/63] target/riscv: vector floating-point merge instructions,
Alistair Francis <=
- [PULL 45/63] target/riscv: widening floating-point/integer type-convert instructions, Alistair Francis, 2020/06/26
- [PULL 24/63] target/riscv: vector widening integer multiply-add instructions, Alistair Francis, 2020/06/26
- [PULL 44/63] target/riscv: vector floating-point/integer type-convert instructions, Alistair Francis, 2020/06/26
- [PULL 29/63] target/riscv: vector widening saturating scaled multiply-add, Alistair Francis, 2020/06/26
- [PULL 30/63] target/riscv: vector single-width scaling shift instructions, Alistair Francis, 2020/06/26
- [PULL 25/63] target/riscv: vector integer merge and move instructions, Alistair Francis, 2020/06/26
- [PULL 46/63] target/riscv: narrowing floating-point/integer type-convert instructions, Alistair Francis, 2020/06/26
- [PULL 31/63] target/riscv: vector narrowing fixed-point clip instructions, Alistair Francis, 2020/06/26
- [PULL 32/63] target/riscv: vector single-width floating-point add/subtract instructions, Alistair Francis, 2020/06/26
- [PULL 26/63] target/riscv: vector single-width saturating add and subtract, Alistair Francis, 2020/06/26