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[PULL 48/63] target/riscv: vector wideing integer reduction instructions
From: |
Alistair Francis |
Subject: |
[PULL 48/63] target/riscv: vector wideing integer reduction instructions |
Date: |
Fri, 26 Jun 2020 14:43:55 -0700 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200623215920.2594-47-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 7 +++++++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 4 ++++
target/riscv/vector_helper.c | 11 +++++++++++
4 files changed, 24 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index a7fe4443e4..1c1277c0d1 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1072,3 +1072,10 @@ DEF_HELPER_6(vredxor_vs_b, void, ptr, ptr, ptr, ptr,
env, i32)
DEF_HELPER_6(vredxor_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vredxor_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vredxor_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vwredsumu_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwredsumu_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwredsumu_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 878eeecb7e..b78fd8bc04 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -539,6 +539,8 @@ vredminu_vs 000100 . ..... ..... 010 ..... 1010111 @r_vm
vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm
vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm
vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm
+vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm
+vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index b4e3f904d3..91fc1fd059 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2342,3 +2342,7 @@ GEN_OPIVV_TRANS(vredmin_vs, reduction_check)
GEN_OPIVV_TRANS(vredand_vs, reduction_check)
GEN_OPIVV_TRANS(vredor_vs, reduction_check)
GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
+
+/* Vector Widening Integer Reduction Instructions */
+GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check)
+GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 1bf3c870d3..bc7624eba3 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4406,3 +4406,14 @@ GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1,
DO_XOR, clearb)
GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR, clearh)
GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR, clearl)
GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR, clearq)
+
+/* Vector Widening Integer Reduction Instructions */
+/* signed sum reduction into double-width accumulator */
+GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD, clearh)
+GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD, clearl)
+GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD, clearq)
+
+/* Unsigned sum reduction into double-width accumulator */
+GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD, clearh)
+GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD, clearl)
+GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD, clearq)
--
2.27.0
- [PULL 44/63] target/riscv: vector floating-point/integer type-convert instructions, (continued)
- [PULL 44/63] target/riscv: vector floating-point/integer type-convert instructions, Alistair Francis, 2020/06/26
- [PULL 29/63] target/riscv: vector widening saturating scaled multiply-add, Alistair Francis, 2020/06/26
- [PULL 30/63] target/riscv: vector single-width scaling shift instructions, Alistair Francis, 2020/06/26
- [PULL 25/63] target/riscv: vector integer merge and move instructions, Alistair Francis, 2020/06/26
- [PULL 46/63] target/riscv: narrowing floating-point/integer type-convert instructions, Alistair Francis, 2020/06/26
- [PULL 31/63] target/riscv: vector narrowing fixed-point clip instructions, Alistair Francis, 2020/06/26
- [PULL 32/63] target/riscv: vector single-width floating-point add/subtract instructions, Alistair Francis, 2020/06/26
- [PULL 26/63] target/riscv: vector single-width saturating add and subtract, Alistair Francis, 2020/06/26
- [PULL 27/63] target/riscv: vector single-width averaging add and subtract, Alistair Francis, 2020/06/26
- [PULL 49/63] target/riscv: vector single-width floating-point reduction instructions, Alistair Francis, 2020/06/26
- [PULL 48/63] target/riscv: vector wideing integer reduction instructions,
Alistair Francis <=
- [PULL 47/63] target/riscv: vector single-width integer reduction instructions, Alistair Francis, 2020/06/26
- [PULL 33/63] target/riscv: vector widening floating-point add/subtract instructions, Alistair Francis, 2020/06/26
- [PULL 51/63] target/riscv: vector mask-register logical instructions, Alistair Francis, 2020/06/26
- [PULL 50/63] target/riscv: vector widening floating-point reduction instructions, Alistair Francis, 2020/06/26
- [PULL 52/63] target/riscv: vector mask population count vmpopc, Alistair Francis, 2020/06/26
- [PULL 53/63] target/riscv: vmfirst find-first-set mask bit, Alistair Francis, 2020/06/26
- [PULL 56/63] target/riscv: vector element index instruction, Alistair Francis, 2020/06/26
- [PULL 54/63] target/riscv: set-X-first mask bit, Alistair Francis, 2020/06/26
- [PULL 55/63] target/riscv: vector iota instruction, Alistair Francis, 2020/06/26
- [PULL 57/63] target/riscv: integer extract instruction, Alistair Francis, 2020/06/26