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Re: [PULL 00/63] riscv-to-apply queue
From: |
Peter Maydell |
Subject: |
Re: [PULL 00/63] riscv-to-apply queue |
Date: |
Sun, 28 Jun 2020 15:30:41 +0100 |
On Fri, 26 Jun 2020 at 22:53, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 553cf5d7c47bee05a3dec9461c1f8430316d516b:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging (2020-06-26
> 18:22:36 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200626-1
>
> for you to fetch changes up to b39d59434ea10649fdb9e0a339c30c76e38c5e17:
>
> target/riscv: configure and turn on vector extension from command line
> (2020-06-26 14:22:15 -0700)
>
> ----------------------------------------------------------------
> This PR contains two patches to improve PLIC support in QEMU.
>
> The rest of the PR is adding support for the v0.7.1 RISC-V vector
> extensions. This is experimental support as the vector extensions are
> still in a draft state.
>
Hi; I'm afraid this fails to build on PPC64 and s390x (ie
our big-endian hosts):
/home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
/home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
/home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
memset(tail & ~(7ULL), 0, part1);
^
/home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
memset((tail + 8) & ~(7ULL), 0, part2);
~~~~~~~~~~ ^
/home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
memset(tail & ~(7ULL), 0, part1);
^
/home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
memset((tail + 8) & ~(7ULL), 0, part2);
~~~~~~~~~~ ^
/home/ubuntu/qemu/rules.mak:69: recipe for target
'target/riscv/vector_helper.o' failed
thanks
-- PMM
- [PULL 55/63] target/riscv: vector iota instruction, (continued)
- [PULL 55/63] target/riscv: vector iota instruction, Alistair Francis, 2020/06/26
- [PULL 57/63] target/riscv: integer extract instruction, Alistair Francis, 2020/06/26
- [PULL 58/63] target/riscv: integer scalar move instruction, Alistair Francis, 2020/06/26
- [PULL 59/63] target/riscv: floating-point scalar move instructions, Alistair Francis, 2020/06/26
- [PULL 60/63] target/riscv: vector slide instructions, Alistair Francis, 2020/06/26
- [PULL 61/63] target/riscv: vector register gather instruction, Alistair Francis, 2020/06/26
- [PULL 62/63] target/riscv: vector compress instruction, Alistair Francis, 2020/06/26
- [PULL 63/63] target/riscv: configure and turn on vector extension from command line, Alistair Francis, 2020/06/26
- Re: [PULL 00/63] riscv-to-apply queue, no-reply, 2020/06/26
- Re: [PULL 00/63] riscv-to-apply queue, no-reply, 2020/06/26
- Re: [PULL 00/63] riscv-to-apply queue,
Peter Maydell <=