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Re: [PATCH v4 4/4] RISC-V: Support 64 bit start address
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v4 4/4] RISC-V: Support 64 bit start address |
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Date: |
Fri, 3 Jul 2020 09:19:18 +0800 |
On Thu, Jul 2, 2020 at 2:39 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> Even though the start address in ROM code is declared as a 64 bit address
> for RV64, it can't be used as upper bits are set to zero in ROM code.
>
> Update the ROM code correctly to reflect the 64bit value.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> hw/riscv/boot.c | 6 +++++-
> hw/riscv/sifive_u.c | 6 +++++-
> 2 files changed, 10 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
- [PATCH v4 0/4] Add OpenSBI dynamic firmware support, Atish Patra, 2020/07/01
- [PATCH v4 1/4] riscv: Unify Qemu's reset vector code path, Atish Patra, 2020/07/01
- [PATCH v4 3/4] riscv: Add opensbi firmware dynamic support, Atish Patra, 2020/07/01
- [PATCH v4 4/4] RISC-V: Support 64 bit start address, Atish Patra, 2020/07/01
- [PATCH v4 2/4] RISC-V: Copy the fdt in dram instead of ROM, Atish Patra, 2020/07/01
- Re: [PATCH v4 0/4] Add OpenSBI dynamic firmware support, Alistair Francis, 2020/07/07