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Re: [PATCH 05/21] target/xtensa: support copying registers up to 64 bits
From: |
Max Filippov |
Subject: |
Re: [PATCH 05/21] target/xtensa: support copying registers up to 64 bits wide |
Date: |
Wed, 8 Jul 2020 10:14:08 -0700 |
On Wed, Jul 8, 2020 at 9:14 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/6/20 4:47 PM, Max Filippov wrote:
> > + if (arg_copy[i].arg->num_bits <= 32) {
> > + temp = tcg_temp_local_new_i32();
> > + tcg_gen_mov_i32(temp, arg_copy[i].arg->in);
> > + } else if (arg_copy[i].arg->num_bits <= 64) {
> > + temp = tcg_temp_local_new_i64();
> > + tcg_gen_mov_i64(temp, arg_copy[i].arg->in);
>
> This shouldn't compile.
>
> You can't assign both TCGv_i32 and TCGv_i64 to the same variable.
>
> What's going on here?
temp is a void pointer, as well as OpcodeArg::in and OpcodeArg::out.
--
Thanks.
-- Max
- Re: [PATCH 03/21] softfloat: add xtensa specialization for pickNaNMulAdd, (continued)
- [PATCH 04/21] target/xtensa: add geometry to xtensa_get_regfile_by_name, Max Filippov, 2020/07/06
- [PATCH 06/21] target/xtensa: rename FPU2000 translators and helpers, Max Filippov, 2020/07/06
- [PATCH 07/21] target/xtensa: move FSR/FCR register accessors, Max Filippov, 2020/07/06
- [PATCH 05/21] target/xtensa: support copying registers up to 64 bits wide, Max Filippov, 2020/07/06
- [PATCH 08/21] target/xtensa: don't access BR regfile directly, Max Filippov, 2020/07/06
- [PATCH 10/21] target/xtensa: implement FPU division and square root, Max Filippov, 2020/07/06
- [PATCH 11/21] tests/tcg/xtensa: fix test execution on ISS, Max Filippov, 2020/07/06
- [PATCH 12/21] tests/tcg/xtensa: update test_fp0_arith for DFPU, Max Filippov, 2020/07/06
- [PATCH 09/21] target/xtensa: add DFP option, registers and opcodes, Max Filippov, 2020/07/06