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[PATCH v3 10/11] hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 suppo
From: |
Eric Auger |
Subject: |
[PATCH v3 10/11] hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 support |
Date: |
Wed, 8 Jul 2020 16:18:55 +0200 |
HAD is a mandatory features with SMMUv3.1 if S1P is set, which is
our case. Other 3.1 mandatory features come with S2P which we don't
have.
So let's support HAD and advertise SMMUv3.1 support in AIDR.
HAD support allows the CD to disable hierarchical attributes, ie.
if the HAD0/1 bit is set, the APTable field of table descriptors
walked through TTB0/1 is ignored.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
hw/arm/smmuv3-internal.h | 2 ++
include/hw/arm/smmu-common.h | 1 +
hw/arm/smmu-common.c | 2 +-
hw/arm/smmuv3.c | 6 +++++-
hw/arm/trace-events | 2 +-
5 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 6296235020..4bc1548dff 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -54,6 +54,7 @@ REG32(IDR1, 0x4)
REG32(IDR2, 0x8)
REG32(IDR3, 0xc)
+ FIELD(IDR3, HAD, 2, 1);
REG32(IDR4, 0x10)
REG32(IDR5, 0x14)
FIELD(IDR5, OAS, 0, 3);
@@ -578,6 +579,7 @@ static inline int pa_range(STE *ste)
lo = (x)->word[(sel) * 2 + 2] & ~0xfULL; \
hi | lo; \
})
+#define CD_HAD(x, sel) extract32((x)->word[(sel) * 2 + 2], 1, 1)
#define CD_TSZ(x, sel) extract32((x)->word[0], (16 * (sel)) + 0, 6)
#define CD_TG(x, sel) extract32((x)->word[0], (16 * (sel)) + 6, 2)
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index 192e8455aa..759e59daa2 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -50,6 +50,7 @@ typedef struct SMMUTransTableInfo {
uint64_t ttb; /* TT base address */
uint8_t tsz; /* input range, ie. 2^(64 -tsz)*/
uint8_t granule_sz; /* granule page shift */
+ bool had; /* hierarchical attribute disable */
} SMMUTransTableInfo;
typedef struct SMMUTLBEntry {
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index aa2c5d76da..f626b8d25e 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -313,7 +313,7 @@ static int smmu_ptw_64(SMMUTransCfg *cfg,
if (is_table_pte(pte, level)) {
ap = PTE_APTABLE(pte);
- if (is_permission_fault(ap, perm)) {
+ if (is_permission_fault(ap, perm) && !tt->had) {
info->type = SMMU_PTW_ERR_PERMISSION;
goto error;
}
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 718f28462e..b262f0e4a7 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -254,6 +254,8 @@ static void smmuv3_init_regs(SMMUv3State *s)
s->idr[1] = FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS);
s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS);
+ s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1);
+
/* 4K and 64K granule support */
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1);
@@ -270,6 +272,7 @@ static void smmuv3_init_regs(SMMUv3State *s)
s->features = 0;
s->sid_split = 0;
+ s->aidr = 0x1;
}
static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
@@ -506,7 +509,8 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd,
SMMUEventInfo *event)
if (tt->ttb & ~(MAKE_64BIT_MASK(0, cfg->oas))) {
goto bad_cd;
}
- trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz);
+ tt->had = CD_HAD(cd, i);
+ trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz,
tt->had);
}
event->record_trans_faults = CD_R(cd);
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index 3d905e0f7d..c8a4d80f6b 100644
--- a/hw/arm/trace-events
+++ b/hw/arm/trace-events
@@ -39,7 +39,7 @@ smmuv3_translate_abort(const char *n, uint16_t sid, uint64_t
addr, bool is_write
smmuv3_translate_success(const char *n, uint16_t sid, uint64_t iova, uint64_t
translated, int perm) "%s sid=%d iova=0x%"PRIx64" translated=0x%"PRIx64"
perm=0x%x"
smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64
smmuv3_decode_cd(uint32_t oas) "oas=%d"
-smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz)
"TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d"
+smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz,
bool had) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d had:%d"
smmuv3_cmdq_cfgi_ste(int streamid) "streamid =%d"
smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%d - end=0x%d"
smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid = %d"
--
2.21.3
- [PATCH v3 00/11] SMMUv3.2 Range-based TLB Invalidation Support, Eric Auger, 2020/07/08
- [PATCH v3 05/11] hw/arm/smmu-common: Manage IOTLB block entries, Eric Auger, 2020/07/08
- [PATCH v3 03/11] hw/arm/smmu: Introduce smmu_get_iotlb_key(), Eric Auger, 2020/07/08
- [PATCH v3 01/11] hw/arm/smmu-common: Factorize some code in smmu_ptw_64(), Eric Auger, 2020/07/08
- [PATCH v3 02/11] hw/arm/smmu-common: Add IOTLB helpers, Eric Auger, 2020/07/08
- [PATCH v3 07/11] hw/arm/smmuv3: Get prepared for range invalidation, Eric Auger, 2020/07/08
- [PATCH v3 04/11] hw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB value, Eric Auger, 2020/07/08
- [PATCH v3 10/11] hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 support,
Eric Auger <=
- [PATCH v3 08/11] hw/arm/smmuv3: Fix IIDR offset, Eric Auger, 2020/07/08
- [PATCH v3 09/11] hw/arm/smmuv3: Let AIDR advertise SMMUv3.0 support, Eric Auger, 2020/07/08
- [PATCH v3 06/11] hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper, Eric Auger, 2020/07/08
- [PATCH v3 11/11] hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation, Eric Auger, 2020/07/08