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[RFC 61/65] fpu: fix float16 nan check
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From: |
frank . chang |
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Subject: |
[RFC 61/65] fpu: fix float16 nan check |
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Date: |
Fri, 10 Jul 2020 18:49:15 +0800 |
From: Chih-Min Chao <chihmin.chao@sifive.com>
16 15 10 0
|sign | exp | mantissa |
qNaN x 11111 1x_xxxx_xxxx
The mask should check exp + msb of mantissa
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
fpu/softfloat-specialize.inc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c
index 44f5b661f8..fe7a5e79e4 100644
--- a/fpu/softfloat-specialize.inc.c
+++ b/fpu/softfloat-specialize.inc.c
@@ -254,7 +254,7 @@ bool float16_is_quiet_nan(float16 a_, float_status *status)
if (snan_bit_is_one(status)) {
return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
} else {
- return ((a & ~0x8000) >= 0x7C80);
+ return ((a & ~0x8000) >= 0x7E00);
}
#endif
}
@@ -271,7 +271,7 @@ bool float16_is_signaling_nan(float16 a_, float_status
*status)
#else
uint16_t a = float16_val(a_);
if (snan_bit_is_one(status)) {
- return ((a & ~0x8000) >= 0x7C80);
+ return ((a & ~0x8000) >= 0x7E00);
} else {
return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
}
--
2.17.1
- [RFC 20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns, (continued)
- [RFC 20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns, frank . chang, 2020/07/10
- [RFC 30/65] target/riscv: rvv-0.9: floating-point scalar move instructions, frank . chang, 2020/07/10
- [RFC 32/65] target/riscv: rvv-0.9: integer extension instructions, frank . chang, 2020/07/10
- [RFC 34/65] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow, frank . chang, 2020/07/10
- [RFC 37/65] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions, frank . chang, 2020/07/10
- [RFC 46/65] target/riscv: rvv-0.9: slide instructions, frank . chang, 2020/07/10
- [RFC 47/65] target/riscv: rvv-0.9: floating-point slide instructions, frank . chang, 2020/07/10
- [RFC 52/65] target/riscv: rvv-0.9: widening floating-point reduction instructions, frank . chang, 2020/07/10
- [RFC 56/65] target/riscv: rvv-0.9: remove integer extract instruction, frank . chang, 2020/07/10
- [RFC 58/65] target/riscv: rvv-0.9: widening floating-point/integer type-convert, frank . chang, 2020/07/10
- [RFC 61/65] fpu: fix float16 nan check,
frank . chang <=
- [RFC 04/65] target/riscv: fix vill bit index in vtype register, frank . chang, 2020/07/10
- [RFC 22/65] target/riscv: rvv-0.9: floating-point square-root instruction, frank . chang, 2020/07/10
- [RFC 23/65] target/riscv: rvv-0.9: floating-point classify instructions, frank . chang, 2020/07/10
- [RFC 24/65] target/riscv: rvv-0.9: mask population count instruction, frank . chang, 2020/07/10
- [RFC 44/65] target/riscv: rvv-0.9: mask-register logical instructions, frank . chang, 2020/07/10
- [RFC 57/65] target/riscv: rvv-0.9: floating-point min/max instructions, frank . chang, 2020/07/10
- [RFC 54/65] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add, frank . chang, 2020/07/10
- [RFC 59/65] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert, frank . chang, 2020/07/10