[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v4 15/22] tests/tcg/xtensa: update test_fp0_conv for DFPU
|
From: |
Max Filippov |
|
Subject: |
[PATCH v4 15/22] tests/tcg/xtensa: update test_fp0_conv for DFPU |
|
Date: |
Sat, 11 Jul 2020 04:06:50 -0700 |
DFPU conversion opcodes update FSR flags. Add FSR parameters and
expected FSR register values for the conversion tests.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/test_fp0_conv.S | 299 ++++++++++++++++---------------
1 file changed, 155 insertions(+), 144 deletions(-)
diff --git a/tests/tcg/xtensa/test_fp0_conv.S b/tests/tcg/xtensa/test_fp0_conv.S
index 147e3d5062df..cfee6e51790c 100644
--- a/tests/tcg/xtensa/test_fp0_conv.S
+++ b/tests/tcg/xtensa/test_fp0_conv.S
@@ -1,4 +1,5 @@
#include "macros.inc"
+#include "fpu.h"
test_suite fp0_conv
@@ -9,7 +10,7 @@ test_suite fp0_conv
wfr \fr, a2
.endm
-.macro test_ftoi_ex op, r0, fr0, v, c, r
+.macro test_ftoi_ex op, r0, fr0, v, c, r, sr
movi a2, 0
wur a2, fsr
movfp \fr0, \v
@@ -18,20 +19,25 @@ test_suite fp0_conv
movi a3, \r
assert eq, \r0, a3
rur a2, fsr
+#if DFPU
+ movi a3, \sr
+ assert eq, a2, a3
+#else
assert eqi, a2, 0
+#endif
.endm
-.macro test_ftoi op, r0, fr0, v, c, r
+.macro test_ftoi op, r0, fr0, v, c, r, sr
movi a2, 0
wur a2, fcr
- test_ftoi_ex \op, \r0, \fr0, \v, \c, \r
+ test_ftoi_ex \op, \r0, \fr0, \v, \c, \r, \sr
movi a2, 0x7c
wur a2, fcr
- test_ftoi_ex \op, \r0, \fr0, \v, \c, \r
+ test_ftoi_ex \op, \r0, \fr0, \v, \c, \r, \sr
.endm
-.macro test_itof_ex op, fr0, ar0, v, c, r
+.macro test_itof_ex op, fr0, ar0, v, c, r, sr
movi a2, 0
wur a2, fsr
movi \ar0, \v
@@ -42,23 +48,28 @@ test_suite fp0_conv
movi a3, \r
assert eq, a2, a3
rur a2, fsr
+#if DFPU
+ movi a3, \sr
+ assert eq, a2, a3
+#else
assert eqi, a2, 0
+#endif
.endm
-.macro test_itof_rm op, fr0, ar0, v, c, rm, r
+.macro test_itof_rm op, fr0, ar0, v, c, rm, r, sr
movi a2, \rm
wur a2, fcr
- test_itof_ex \op, \fr0, \ar0, \v, \c, \r
+ test_itof_ex \op, \fr0, \ar0, \v, \c, \r, \sr
movi a2, (\rm) | 0x7c
wur a2, fcr
- test_itof_ex \op, \fr0, \ar0, \v, \c, \r
+ test_itof_ex \op, \fr0, \ar0, \v, \c, \r, \sr
.endm
-.macro test_itof op, fr0, ar0, v, c, r0, r1, r2, r3
- test_itof_rm \op, \fr0, \ar0, \v, \c, 0, \r0
- test_itof_rm \op, \fr0, \ar0, \v, \c, 1, \r1
- test_itof_rm \op, \fr0, \ar0, \v, \c, 2, \r2
- test_itof_rm \op, \fr0, \ar0, \v, \c, 3, \r3
+.macro test_itof op, fr0, ar0, v, c, r0, r1, r2, r3, sr
+ test_itof_rm \op, \fr0, \ar0, \v, \c, 0, \r0, \sr
+ test_itof_rm \op, \fr0, \ar0, \v, \c, 1, \r1, \sr
+ test_itof_rm \op, \fr0, \ar0, \v, \c, 2, \r2, \sr
+ test_itof_rm \op, \fr0, \ar0, \v, \c, 3, \r3, \sr
.endm
test round_s
@@ -66,237 +77,237 @@ test round_s
wsr a2, cpenable
/* NaN */
- test_ftoi round.s, a2, f0, 0xffc00001, 0, 0x7fffffff
- test_ftoi round.s, a2, f0, 0xff800001, 0, 0x7fffffff
+ test_ftoi round.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V
+ test_ftoi round.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V
/* -inf */
- test_ftoi round.s, a2, f0, 0xff800000, 0, 0x80000000
+ test_ftoi round.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V
/* negative overflow */
- test_ftoi round.s, a2, f0, 0xceffffff, 1, 0x80000000
- test_ftoi round.s, a2, f0, 0xcf000000, 0, 0x80000000
- test_ftoi round.s, a2, f0, 0xceffffff, 0, 0x80000080
+ test_ftoi round.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V
+ test_ftoi round.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__
+ test_ftoi round.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__
/* negative */
- test_ftoi round.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */
- test_ftoi round.s, a2, f0, 0xbfc00000, 0, -2 /* -1.5 */
- test_ftoi round.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
- test_ftoi round.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
- test_ftoi round.s, a2, f0, 0xbf400000, 0, -1 /* -0.75 */
- test_ftoi round.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */
+ test_ftoi round.s, a2, f0, 0xbfa00000, 1, -2, FSR_I /* -1.25 * 2 */
+ test_ftoi round.s, a2, f0, 0xbfc00000, 0, -2, FSR_I /* -1.5 */
+ test_ftoi round.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */
+ test_ftoi round.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */
+ test_ftoi round.s, a2, f0, 0xbf400000, 0, -1, FSR_I /* -0.75 */
+ test_ftoi round.s, a2, f0, 0xbf000000, 0, 0, FSR_I /* -0.5 */
/* positive */
- test_ftoi round.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */
- test_ftoi round.s, a2, f0, 0x3f400000, 0, 1 /* 0.75 */
- test_ftoi round.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
- test_ftoi round.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
- test_ftoi round.s, a2, f0, 0x3fc00000, 0, 2 /* 1.5 */
- test_ftoi round.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */
+ test_ftoi round.s, a2, f0, 0x3f000000, 0, 0, FSR_I /* 0.5 */
+ test_ftoi round.s, a2, f0, 0x3f400000, 0, 1, FSR_I /* 0.75 */
+ test_ftoi round.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */
+ test_ftoi round.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */
+ test_ftoi round.s, a2, f0, 0x3fc00000, 0, 2, FSR_I /* 1.5 */
+ test_ftoi round.s, a2, f0, 0x3fa00000, 1, 2, FSR_I /* 1.25 * 2 */
/* positive overflow */
- test_ftoi round.s, a2, f0, 0x4effffff, 0, 0x7fffff80
- test_ftoi round.s, a2, f0, 0x4f000000, 0, 0x7fffffff
- test_ftoi round.s, a2, f0, 0x4effffff, 1, 0x7fffffff
+ test_ftoi round.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__
+ test_ftoi round.s, a2, f0, 0x4f000000, 0, 0x7fffffff, FSR_V
+ test_ftoi round.s, a2, f0, 0x4effffff, 1, 0x7fffffff, FSR_V
/* +inf */
- test_ftoi round.s, a2, f0, 0x7f800000, 0, 0x7fffffff
+ test_ftoi round.s, a2, f0, 0x7f800000, 0, 0x7fffffff, FSR_V
/* NaN */
- test_ftoi round.s, a2, f0, 0x7f800001, 0, 0x7fffffff
- test_ftoi round.s, a2, f0, 0x7fc00000, 0, 0x7fffffff
+ test_ftoi round.s, a2, f0, 0x7f800001, 0, 0x7fffffff, FSR_V
+ test_ftoi round.s, a2, f0, 0x7fc00000, 0, 0x7fffffff, FSR_V
test_end
test trunc_s
/* NaN */
- test_ftoi trunc.s, a2, f0, 0xffc00001, 0, 0x7fffffff
- test_ftoi trunc.s, a2, f0, 0xff800001, 0, 0x7fffffff
+ test_ftoi trunc.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V
+ test_ftoi trunc.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V
/* -inf */
- test_ftoi trunc.s, a2, f0, 0xff800000, 0, 0x80000000
+ test_ftoi trunc.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V
/* negative overflow */
- test_ftoi trunc.s, a2, f0, 0xceffffff, 1, 0x80000000
- test_ftoi trunc.s, a2, f0, 0xcf000000, 0, 0x80000000
- test_ftoi trunc.s, a2, f0, 0xceffffff, 0, 0x80000080
+ test_ftoi trunc.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V
+ test_ftoi trunc.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__
+ test_ftoi trunc.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__
/* negative */
- test_ftoi trunc.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */
- test_ftoi trunc.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */
- test_ftoi trunc.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
- test_ftoi trunc.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
- test_ftoi trunc.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */
- test_ftoi trunc.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */
+ test_ftoi trunc.s, a2, f0, 0xbfa00000, 1, -2, FSR_I /* -1.25 * 2 */
+ test_ftoi trunc.s, a2, f0, 0xbfc00000, 0, -1, FSR_I /* -1.5 */
+ test_ftoi trunc.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */
+ test_ftoi trunc.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */
+ test_ftoi trunc.s, a2, f0, 0xbf400000, 0, 0, FSR_I /* -0.75 */
+ test_ftoi trunc.s, a2, f0, 0xbf000000, 0, 0, FSR_I /* -0.5 */
/* positive */
- test_ftoi trunc.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */
- test_ftoi trunc.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */
- test_ftoi trunc.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
- test_ftoi trunc.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
- test_ftoi trunc.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */
- test_ftoi trunc.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */
+ test_ftoi trunc.s, a2, f0, 0x3f000000, 0, 0, FSR_I /* 0.5 */
+ test_ftoi trunc.s, a2, f0, 0x3f400000, 0, 0, FSR_I /* 0.75 */
+ test_ftoi trunc.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */
+ test_ftoi trunc.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */
+ test_ftoi trunc.s, a2, f0, 0x3fc00000, 0, 1, FSR_I /* 1.5 */
+ test_ftoi trunc.s, a2, f0, 0x3fa00000, 1, 2, FSR_I /* 1.25 * 2 */
/* positive overflow */
- test_ftoi trunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80
- test_ftoi trunc.s, a2, f0, 0x4f000000, 0, 0x7fffffff
- test_ftoi trunc.s, a2, f0, 0x4effffff, 1, 0x7fffffff
+ test_ftoi trunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__
+ test_ftoi trunc.s, a2, f0, 0x4f000000, 0, 0x7fffffff, FSR_V
+ test_ftoi trunc.s, a2, f0, 0x4effffff, 1, 0x7fffffff, FSR_V
/* +inf */
- test_ftoi trunc.s, a2, f0, 0x7f800000, 0, 0x7fffffff
+ test_ftoi trunc.s, a2, f0, 0x7f800000, 0, 0x7fffffff, FSR_V
/* NaN */
- test_ftoi trunc.s, a2, f0, 0x7f800001, 0, 0x7fffffff
- test_ftoi trunc.s, a2, f0, 0x7fc00000, 0, 0x7fffffff
+ test_ftoi trunc.s, a2, f0, 0x7f800001, 0, 0x7fffffff, FSR_V
+ test_ftoi trunc.s, a2, f0, 0x7fc00000, 0, 0x7fffffff, FSR_V
test_end
test floor_s
/* NaN */
- test_ftoi floor.s, a2, f0, 0xffc00001, 0, 0x7fffffff
- test_ftoi floor.s, a2, f0, 0xff800001, 0, 0x7fffffff
+ test_ftoi floor.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V
+ test_ftoi floor.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V
/* -inf */
- test_ftoi floor.s, a2, f0, 0xff800000, 0, 0x80000000
+ test_ftoi floor.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V
/* negative overflow */
- test_ftoi floor.s, a2, f0, 0xceffffff, 1, 0x80000000
- test_ftoi floor.s, a2, f0, 0xcf000000, 0, 0x80000000
- test_ftoi floor.s, a2, f0, 0xceffffff, 0, 0x80000080
+ test_ftoi floor.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V
+ test_ftoi floor.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__
+ test_ftoi floor.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__
/* negative */
- test_ftoi floor.s, a2, f0, 0xbfa00000, 1, -3 /* -1.25 * 2 */
- test_ftoi floor.s, a2, f0, 0xbfc00000, 0, -2 /* -1.5 */
- test_ftoi floor.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
- test_ftoi floor.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
- test_ftoi floor.s, a2, f0, 0xbf400000, 0, -1 /* -0.75 */
- test_ftoi floor.s, a2, f0, 0xbf000000, 0, -1 /* -0.5 */
+ test_ftoi floor.s, a2, f0, 0xbfa00000, 1, -3, FSR_I /* -1.25 * 2 */
+ test_ftoi floor.s, a2, f0, 0xbfc00000, 0, -2, FSR_I /* -1.5 */
+ test_ftoi floor.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */
+ test_ftoi floor.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */
+ test_ftoi floor.s, a2, f0, 0xbf400000, 0, -1, FSR_I /* -0.75 */
+ test_ftoi floor.s, a2, f0, 0xbf000000, 0, -1, FSR_I /* -0.5 */
/* positive */
- test_ftoi floor.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */
- test_ftoi floor.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */
- test_ftoi floor.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
- test_ftoi floor.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
- test_ftoi floor.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */
- test_ftoi floor.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */
+ test_ftoi floor.s, a2, f0, 0x3f000000, 0, 0, FSR_I /* 0.5 */
+ test_ftoi floor.s, a2, f0, 0x3f400000, 0, 0, FSR_I /* 0.75 */
+ test_ftoi floor.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */
+ test_ftoi floor.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */
+ test_ftoi floor.s, a2, f0, 0x3fc00000, 0, 1, FSR_I /* 1.5 */
+ test_ftoi floor.s, a2, f0, 0x3fa00000, 1, 2, FSR_I /* 1.25 * 2 */
/* positive overflow */
- test_ftoi floor.s, a2, f0, 0x4effffff, 0, 0x7fffff80
- test_ftoi floor.s, a2, f0, 0x4f000000, 0, 0x7fffffff
- test_ftoi floor.s, a2, f0, 0x4effffff, 1, 0x7fffffff
+ test_ftoi floor.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__
+ test_ftoi floor.s, a2, f0, 0x4f000000, 0, 0x7fffffff, FSR_V
+ test_ftoi floor.s, a2, f0, 0x4effffff, 1, 0x7fffffff, FSR_V
/* +inf */
- test_ftoi floor.s, a2, f0, 0x7f800000, 0, 0x7fffffff
+ test_ftoi floor.s, a2, f0, 0x7f800000, 0, 0x7fffffff, FSR_V
/* NaN */
- test_ftoi floor.s, a2, f0, 0x7f800001, 0, 0x7fffffff
- test_ftoi floor.s, a2, f0, 0x7fc00000, 0, 0x7fffffff
+ test_ftoi floor.s, a2, f0, 0x7f800001, 0, 0x7fffffff, FSR_V
+ test_ftoi floor.s, a2, f0, 0x7fc00000, 0, 0x7fffffff, FSR_V
test_end
test ceil_s
/* NaN */
- test_ftoi ceil.s, a2, f0, 0xffc00001, 0, 0x7fffffff
- test_ftoi ceil.s, a2, f0, 0xff800001, 0, 0x7fffffff
+ test_ftoi ceil.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V
+ test_ftoi ceil.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V
/* -inf */
- test_ftoi ceil.s, a2, f0, 0xff800000, 0, 0x80000000
+ test_ftoi ceil.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V
/* negative overflow */
- test_ftoi ceil.s, a2, f0, 0xceffffff, 1, 0x80000000
- test_ftoi ceil.s, a2, f0, 0xcf000000, 0, 0x80000000
- test_ftoi ceil.s, a2, f0, 0xceffffff, 0, 0x80000080
+ test_ftoi ceil.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V
+ test_ftoi ceil.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__
+ test_ftoi ceil.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__
/* negative */
- test_ftoi ceil.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */
- test_ftoi ceil.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */
- test_ftoi ceil.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
- test_ftoi ceil.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
- test_ftoi ceil.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */
- test_ftoi ceil.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */
+ test_ftoi ceil.s, a2, f0, 0xbfa00000, 1, -2, FSR_I /* -1.25 * 2 */
+ test_ftoi ceil.s, a2, f0, 0xbfc00000, 0, -1, FSR_I /* -1.5 */
+ test_ftoi ceil.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */
+ test_ftoi ceil.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */
+ test_ftoi ceil.s, a2, f0, 0xbf400000, 0, 0, FSR_I /* -0.75 */
+ test_ftoi ceil.s, a2, f0, 0xbf000000, 0, 0, FSR_I /* -0.5 */
/* positive */
- test_ftoi ceil.s, a2, f0, 0x3f000000, 0, 1 /* 0.5 */
- test_ftoi ceil.s, a2, f0, 0x3f400000, 0, 1 /* 0.75 */
- test_ftoi ceil.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
- test_ftoi ceil.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
- test_ftoi ceil.s, a2, f0, 0x3fc00000, 0, 2 /* 1.5 */
- test_ftoi ceil.s, a2, f0, 0x3fa00000, 1, 3 /* 1.25 * 2 */
+ test_ftoi ceil.s, a2, f0, 0x3f000000, 0, 1, FSR_I /* 0.5 */
+ test_ftoi ceil.s, a2, f0, 0x3f400000, 0, 1, FSR_I /* 0.75 */
+ test_ftoi ceil.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */
+ test_ftoi ceil.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */
+ test_ftoi ceil.s, a2, f0, 0x3fc00000, 0, 2, FSR_I /* 1.5 */
+ test_ftoi ceil.s, a2, f0, 0x3fa00000, 1, 3, FSR_I /* 1.25 * 2 */
/* positive overflow */
- test_ftoi ceil.s, a2, f0, 0x4effffff, 0, 0x7fffff80
- test_ftoi ceil.s, a2, f0, 0x4f000000, 0, 0x7fffffff
- test_ftoi ceil.s, a2, f0, 0x4effffff, 1, 0x7fffffff
+ test_ftoi ceil.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__
+ test_ftoi ceil.s, a2, f0, 0x4f000000, 0, 0x7fffffff, FSR_V
+ test_ftoi ceil.s, a2, f0, 0x4effffff, 1, 0x7fffffff, FSR_V
/* +inf */
- test_ftoi ceil.s, a2, f0, 0x7f800000, 0, 0x7fffffff
+ test_ftoi ceil.s, a2, f0, 0x7f800000, 0, 0x7fffffff, FSR_V
/* NaN */
- test_ftoi ceil.s, a2, f0, 0x7f800001, 0, 0x7fffffff
- test_ftoi ceil.s, a2, f0, 0x7fc00000, 0, 0x7fffffff
+ test_ftoi ceil.s, a2, f0, 0x7f800001, 0, 0x7fffffff, FSR_V
+ test_ftoi ceil.s, a2, f0, 0x7fc00000, 0, 0x7fffffff, FSR_V
test_end
test utrunc_s
/* NaN */
- test_ftoi utrunc.s, a2, f0, 0xffc00001, 0, 0xffffffff
- test_ftoi utrunc.s, a2, f0, 0xff800001, 0, 0xffffffff
+ test_ftoi utrunc.s, a2, f0, 0xffc00001, 0, 0xffffffff, FSR_V
+ test_ftoi utrunc.s, a2, f0, 0xff800001, 0, 0xffffffff, FSR_V
/* -inf */
- test_ftoi utrunc.s, a2, f0, 0xff800000, 0, 0x80000000
+ test_ftoi utrunc.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V
/* negative overflow */
- test_ftoi utrunc.s, a2, f0, 0xceffffff, 1, 0x80000000
- test_ftoi utrunc.s, a2, f0, 0xcf000000, 0, 0x80000000
- test_ftoi utrunc.s, a2, f0, 0xceffffff, 0, 0x80000080
+ test_ftoi utrunc.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V
+ test_ftoi utrunc.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR_V
+ test_ftoi utrunc.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR_V
/* negative */
- test_ftoi utrunc.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */
- test_ftoi utrunc.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */
- test_ftoi utrunc.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
- test_ftoi utrunc.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
- test_ftoi utrunc.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */
- test_ftoi utrunc.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */
+ test_ftoi utrunc.s, a2, f0, 0xbfa00000, 1, -2, FSR_V /* -1.25 * 2 */
+ test_ftoi utrunc.s, a2, f0, 0xbfc00000, 0, -1, FSR_V /* -1.5 */
+ test_ftoi utrunc.s, a2, f0, 0xbf800000, 1, -2, FSR_V /* -1 * 2 */
+ test_ftoi utrunc.s, a2, f0, 0xbf800000, 0, -1, FSR_V /* -1 */
+ test_ftoi utrunc.s, a2, f0, 0xbf400000, 0, 0, FSR_I /* -0.75 */
+ test_ftoi utrunc.s, a2, f0, 0xbf000000, 0, 0, FSR_I /* -0.5 */
/* positive */
- test_ftoi utrunc.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */
- test_ftoi utrunc.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */
- test_ftoi utrunc.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
- test_ftoi utrunc.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
- test_ftoi utrunc.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */
- test_ftoi utrunc.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */
+ test_ftoi utrunc.s, a2, f0, 0x3f000000, 0, 0, FSR_I /* 0.5 */
+ test_ftoi utrunc.s, a2, f0, 0x3f400000, 0, 0, FSR_I /* 0.75 */
+ test_ftoi utrunc.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */
+ test_ftoi utrunc.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */
+ test_ftoi utrunc.s, a2, f0, 0x3fc00000, 0, 1, FSR_I /* 1.5 */
+ test_ftoi utrunc.s, a2, f0, 0x3fa00000, 1, 2, FSR_I /* 1.25 * 2 */
/* positive overflow */
- test_ftoi utrunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80
- test_ftoi utrunc.s, a2, f0, 0x4f000000, 0, 0x80000000
- test_ftoi utrunc.s, a2, f0, 0x4effffff, 1, 0xffffff00
- test_ftoi utrunc.s, a2, f0, 0x4f800000, 1, 0xffffffff
+ test_ftoi utrunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__
+ test_ftoi utrunc.s, a2, f0, 0x4f000000, 0, 0x80000000, FSR__
+ test_ftoi utrunc.s, a2, f0, 0x4effffff, 1, 0xffffff00, FSR__
+ test_ftoi utrunc.s, a2, f0, 0x4f800000, 1, 0xffffffff, FSR_V
/* +inf */
- test_ftoi utrunc.s, a2, f0, 0x7f800000, 0, 0xffffffff
+ test_ftoi utrunc.s, a2, f0, 0x7f800000, 0, 0xffffffff, FSR_V
/* NaN */
- test_ftoi utrunc.s, a2, f0, 0x7f800001, 0, 0xffffffff
- test_ftoi utrunc.s, a2, f0, 0x7fc00000, 0, 0xffffffff
+ test_ftoi utrunc.s, a2, f0, 0x7f800001, 0, 0xffffffff, FSR_V
+ test_ftoi utrunc.s, a2, f0, 0x7fc00000, 0, 0xffffffff, FSR_V
test_end
test float_s
test_itof float.s, f0, a2, -1, 0, \
- 0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000
- test_itof float.s, f0, a2, 0, 0, 0, 0, 0, 0
+ 0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000, FSR__
+ test_itof float.s, f0, a2, 0, 0, 0, 0, 0, 0, FSR__
test_itof float.s, f0, a2, 1, 1, \
- 0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000
+ 0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000, FSR__
test_itof float.s, f0, a2, 1, 0, \
- 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000
+ 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, FSR__
test_itof float.s, f0, a2, 0x7fffffff, 0, \
- 0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff
+ 0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff, FSR_I
test_end
test ufloat_s
- test_itof ufloat.s, f0, a2, 0, 0, 0, 0, 0, 0
+ test_itof ufloat.s, f0, a2, 0, 0, 0, 0, 0, 0, FSR__
test_itof ufloat.s, f0, a2, 1, 1, \
- 0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000
+ 0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000, FSR__
test_itof ufloat.s, f0, a2, 1, 0, \
- 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000
+ 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, FSR__
test_itof ufloat.s, f0, a2, 0x7fffffff, 0, \
- 0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff
+ 0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff, FSR_I
test_itof ufloat.s, f0, a2, 0xffffffff, 0, \
- 0x4f800000, 0x4f7fffff, 0x4f800000, 0x4f7fffff
+ 0x4f800000, 0x4f7fffff, 0x4f800000, 0x4f7fffff, FSR_I
test_end
#endif
--
2.20.1
- [PATCH v4 06/22] target/xtensa: rename FPU2000 translators and helpers, (continued)
- [PATCH v4 06/22] target/xtensa: rename FPU2000 translators and helpers, Max Filippov, 2020/07/11
- [PATCH v4 07/22] target/xtensa: move FSR/FCR register accessors, Max Filippov, 2020/07/11
- [PATCH v4 08/22] target/xtensa: don't access BR regfile directly, Max Filippov, 2020/07/11
- [PATCH v4 09/22] target/xtensa: add DFPU option, Max Filippov, 2020/07/11
- [PATCH v4 11/22] target/xtensa: implement FPU division and square root, Max Filippov, 2020/07/11
- [PATCH v4 12/22] tests/tcg/xtensa: fix test execution on ISS, Max Filippov, 2020/07/11
- [PATCH v4 13/22] tests/tcg/xtensa: update test_fp0_arith for DFPU, Max Filippov, 2020/07/11
- [PATCH v4 14/22] tests/tcg/xtensa: expand madd tests, Max Filippov, 2020/07/11
- [PATCH v4 16/22] tests/tcg/xtensa: update test_fp1 for DFPU, Max Filippov, 2020/07/11
- [PATCH v4 10/22] target/xtensa: add DFPU registers and opcodes, Max Filippov, 2020/07/11
- [PATCH v4 15/22] tests/tcg/xtensa: update test_fp0_conv for DFPU,
Max Filippov <=
- [PATCH v4 18/22] tests/tcg/xtensa: add fp0 div and sqrt tests, Max Filippov, 2020/07/11
- [PATCH v4 19/22] tests/tcg/xtensa: test double precision load/store, Max Filippov, 2020/07/11
- [PATCH v4 20/22] tests/tcg/xtensa: add DFP0 arithmetic tests, Max Filippov, 2020/07/11
- [PATCH v4 17/22] tests/tcg/xtensa: update test_lsc for DFPU, Max Filippov, 2020/07/11