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[PULL 01/15] MAINTAINERS: Add an entry for OpenSBI firmware
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From: |
Alistair Francis |
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Subject: |
[PULL 01/15] MAINTAINERS: Add an entry for OpenSBI firmware |
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Date: |
Mon, 13 Jul 2020 17:32:40 -0700 |
From: Bin Meng <bmeng.cn@gmail.com>
List me as the maintainer for OpenSBI firmware related files.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <1593177220-28143-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index fe8139f367..80fa8837e9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2681,6 +2681,13 @@ F: hw/i386/intel_iommu.c
F: hw/i386/intel_iommu_internal.h
F: include/hw/i386/intel_iommu.h
+OpenSBI Firmware
+M: Bin Meng <bmeng.cn@gmail.com>
+S: Supported
+F: pc-bios/opensbi-*
+F: .gitlab-ci.d/opensbi.yml
+F: .gitlab-ci.d/opensbi/
+
Usermode Emulation
------------------
Overall usermode emulation
--
2.27.0
- [PULL 00/15] riscv-to-apply queue, Alistair Francis, 2020/07/13
- [PULL 01/15] MAINTAINERS: Add an entry for OpenSBI firmware,
Alistair Francis <=
- [PULL 02/15] hw/riscv: virt: Sort the SoC memmap table entries, Alistair Francis, 2020/07/13
- [PULL 04/15] RISC-V: Copy the fdt in dram instead of ROM, Alistair Francis, 2020/07/13
- [PULL 03/15] riscv: Unify Qemu's reset vector code path, Alistair Francis, 2020/07/13
- [PULL 05/15] riscv: Add opensbi firmware dynamic support, Alistair Francis, 2020/07/13
- [PULL 06/15] RISC-V: Support 64 bit start address, Alistair Francis, 2020/07/13
- [PULL 07/15] hw/riscv: Modify MROM size to end at 0x10000, Alistair Francis, 2020/07/13
- [PULL 08/15] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion, Alistair Francis, 2020/07/13
- [PULL 09/15] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(), Alistair Francis, 2020/07/13
- [PULL 10/15] target/riscv: fix return value of do_opivx_widen(), Alistair Francis, 2020/07/13
- [PULL 11/15] target/riscv: fix vill bit index in vtype register, Alistair Francis, 2020/07/13