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[PULL 5/5] target/riscv: Fix the range of pmpcfg of CSR funcion table
From: |
Alistair Francis |
Subject: |
[PULL 5/5] target/riscv: Fix the range of pmpcfg of CSR funcion table |
Date: |
Wed, 22 Jul 2020 09:48:38 -0700 |
From: Zong Li <zong.li@sifive.com>
The range of Physical Memory Protection should be from CSR_PMPCFG0
to CSR_PMPCFG3, not to CSR_PMPADDR9.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Message-Id:
<eae49e9252c9596e4f3bdb471772f79235141a87.1595335112.git.zong.li@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ac01c835e1..6a96a01b1c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1353,7 +1353,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTINST] = { hmode, read_mtinst, write_mtinst
},
/* Physical Memory Protection */
- [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
+ [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
/* Performance Counters */
--
2.27.0
- [PULL 0/5] riscv-to-apply queue, Alistair Francis, 2020/07/22
- [PULL 1/5] goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH, Alistair Francis, 2020/07/22
- [PULL 2/5] target/riscv: Quiet Coverity complains about vamo*, Alistair Francis, 2020/07/22
- [PULL 4/5] hw/riscv: sifive_e: Correct debug block size, Alistair Francis, 2020/07/22
- [PULL 3/5] target/riscv: fix vector index load/store constraints, Alistair Francis, 2020/07/22
- [PULL 5/5] target/riscv: Fix the range of pmpcfg of CSR funcion table,
Alistair Francis <=
- Re: [PULL 0/5] riscv-to-apply queue, Peter Maydell, 2020/07/24