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Re: [PATCH v5 3/6] target/ppc: add vmulh{su}w instructions
From: |
David Gibson |
Subject: |
Re: [PATCH v5 3/6] target/ppc: add vmulh{su}w instructions |
Date: |
Mon, 27 Jul 2020 16:32:55 +1000 |
On Fri, Jul 24, 2020 at 10:57:51AM -0700, Richard Henderson wrote:
> On 7/23/20 9:58 PM, Lijun Pan wrote:
> > vmulhsw: Vector Multiply High Signed Word
> > vmulhuw: Vector Multiply High Unsigned Word
> >
> > Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
> > ---
> > v4/v5: no change
> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> > v3: inline the helper_vmulh{su}w multiply directly instead of using macro
> > v2: fix coding style
> > use Power ISA 3.1 flag
>
> The Reviewed-by tag goes above the "---" marker so that it is included when
> the
> patch is applied.
Right, but I've fixed it up on this occasion.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions, Lijun Pan, 2020/07/24
- [PATCH v5 3/6] target/ppc: add vmulh{su}w instructions, Lijun Pan, 2020/07/24
- [PATCH v5 5/6] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions, Lijun Pan, 2020/07/24
- [PATCH v5 2/6] target/ppc: add vmulld to INDEX_op_mul_vec case, Lijun Pan, 2020/07/24
- Re: [PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions, David Gibson, 2020/07/27