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[Bug 1879587] Re: Register number in ESR is incorrect for certain banked

From: Julien Freche
Subject: [Bug 1879587] Re: Register number in ESR is incorrect for certain banked registers when switching from AA32 to AA64
Date: Tue, 04 Aug 2020 19:00:27 -0000

Unfortunately, I won't be able to send the code or binary for the
hypervisor as of now (it will become available at some point in the
future though). I've done a bit of debugging on the QEMU code and it
seems like the approach you are taking works fine in general but the
register mapping code doesn't seem quite right. Applying this patch (on
top of yours):

>From e2182581dcdeedc2cb88cd21b88b4db744677737 Mon Sep 17 00:00:00 2001
From: Julien Freche <julien@bedrocksystems.com>
Date: Tue, 4 Aug 2020 11:54:49 -0700
Subject: [PATCH] Possible fix

 target/arm/helper.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 60b80228fd..455c92b891 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9619,17 +9619,16 @@ static int aarch64_regnum(CPUARMState *env, int 
         switch (mode) {
         case ARM_CPU_MODE_USR:
         case ARM_CPU_MODE_SYS:
-            return 14;
         case ARM_CPU_MODE_HYP:
-            return 16;
+            return 14;
         case ARM_CPU_MODE_IRQ:
-            return 18;
+            return 16;
         case ARM_CPU_MODE_SVC:
-            return 20;
+            return 18;
         case ARM_CPU_MODE_ABT:
-            return 22;
+            return 20;
         case ARM_CPU_MODE_UND:
-            return 24;
+            return 22;
         case ARM_CPU_MODE_FIQ:
             return 30;

Based on the ARM documentation, I would think that LR_svc maps to X18,
not X20. I fixed the ones that seemed wrong but I haven't check every
possible case so you may want to double check this. With the patch I was
able to boot Linux correctly.

Let me know if that makes sense

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  Register number in ESR is incorrect for certain banked registers when
  switching from AA32 to AA64

Status in QEMU:
  In Progress

Bug description:
  I am running into a situation where I have:
  - A hypervisor running in EL2, AA64
  - A guest running in EL1, AA32

  We trap certain accesses to special registers such as DACR (via
  HCR.TVM). One instruction that is trapped is:

  ee03ef10  ->    mcr     15, 0, lr, cr3, cr0, {0}

  The guest is running in SVC mode. So, LR should refer to LR_svc there.
  LR_svc is mapped to X18 in AA64. So, ESR should reflect that. However,
  the actual ESR value is: 0xfe00dc0

  If we decode the 'rt':
  >>> (0xfe00dc0 >> 5) & 0x1f

  My understanding is that 14 is incorrect in the context of AA64. rt
  should be set to 18. The current mode being SVC, LR refers to LR_svc
  not LR_usr. In other words, the mapping between registers in AA64 and
  AA32 doesn't seem to be accounted for. I've tested this with Qemu

  Let me know if that makes sense and if you would like more info. I am also 
happy to test patches.
  Thanks for all the great work on Qemu!

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