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[PULL 03/20] target/riscv: Generate nanboxed results from trans_rvf.inc.
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From: |
Alistair Francis |
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Subject: |
[PULL 03/20] target/riscv: Generate nanboxed results from trans_rvf.inc.c |
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Date: |
Wed, 12 Aug 2020 15:30:28 -0700 |
From: Richard Henderson <richard.henderson@linaro.org>
Make sure that all results from inline single-precision scalar
operations are properly nan-boxed to 64-bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-4-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvf.inc.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c
b/target/riscv/insn_trans/trans_rvf.inc.c
index c7057482e8..264d3139f1 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -167,6 +167,7 @@ static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)
tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1],
0, 31);
}
+ gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
mark_fs_dirty(ctx);
return true;
}
@@ -183,6 +184,7 @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s
*a)
tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31);
tcg_temp_free_i64(t0);
}
+ gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
mark_fs_dirty(ctx);
return true;
}
@@ -199,6 +201,7 @@ static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s
*a)
tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
tcg_temp_free_i64(t0);
}
+ gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
mark_fs_dirty(ctx);
return true;
}
@@ -369,6 +372,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
#else
tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
#endif
+ gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
mark_fs_dirty(ctx);
tcg_temp_free(t0);
--
2.27.0
[PULL 03/20] target/riscv: Generate nanboxed results from trans_rvf.inc.c,
Alistair Francis <=
[PULL 02/20] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s, Alistair Francis, 2020/08/12
[PULL 04/20] target/riscv: Check nanboxed inputs to fp helpers, Alistair Francis, 2020/08/12
[PULL 06/20] target/riscv: Clean up fmv.w.x, Alistair Francis, 2020/08/12
[PULL 09/20] riscv: Fix bug in setting pmpcfg CSR for RISCV64, Alistair Francis, 2020/08/12
[PULL 15/20] gitlab-ci/opensbi: Update GitLab CI to build generic platform, Alistair Francis, 2020/08/12
[PULL 08/20] hw/riscv: sifive_u: Add a dummy L2 cache controller device, Alistair Francis, 2020/08/12
[PULL 12/20] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware, Alistair Francis, 2020/08/12
[PULL 07/20] target/riscv: check before allocating TCG temps, Alistair Francis, 2020/08/12
[PULL 16/20] target/riscv: Fix the translation of physical address, Alistair Francis, 2020/08/12
[PULL 11/20] roms/opensbi: Upgrade from v0.7 to v0.8, Alistair Francis, 2020/08/12