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[PULL 21/35] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn
From: |
Peter Maydell |
Subject: |
[PULL 21/35] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn |
Date: |
Fri, 28 Aug 2020 10:23:59 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Model gen_gvec_fn_zzz on gen_gvec_fn3 in translate-a64.c, but
indicating which kind of register and in which order.
Model do_zzz_fn on the other do_foo functions that take an
argument set and verify sve enabled.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-sve.c | 43 +++++++++++++++++++++-----------------
1 file changed, 24 insertions(+), 19 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index f1803eb72bf..9a3d060c052 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -153,16 +153,13 @@ static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn
*gvec_fn,
}
/* Invoke a vector expander on three Zregs. */
-static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
- int esz, int rd, int rn, int rm)
+static void gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
+ int esz, int rd, int rn, int rm)
{
- if (sve_access_check(s)) {
- unsigned vsz = vec_full_reg_size(s);
- gvec_fn(esz, vec_full_reg_offset(s, rd),
- vec_full_reg_offset(s, rn),
- vec_full_reg_offset(s, rm), vsz, vsz);
- }
- return true;
+ unsigned vsz = vec_full_reg_size(s);
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm), vsz, vsz);
}
/* Invoke a vector move on two Zregs. */
@@ -274,24 +271,32 @@ const uint64_t pred_esz_masks[4] = {
*** SVE Logical - Unpredicated Group
*/
+static bool do_zzz_fn(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *gvec_fn)
+{
+ if (sve_access_check(s)) {
+ gen_gvec_fn_zzz(s, gvec_fn, a->esz, a->rd, a->rn, a->rm);
+ }
+ return true;
+}
+
static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
{
- return do_vector3_z(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm);
+ return do_zzz_fn(s, a, tcg_gen_gvec_and);
}
static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
{
- return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
+ return do_zzz_fn(s, a, tcg_gen_gvec_or);
}
static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
{
- return do_vector3_z(s, tcg_gen_gvec_xor, 0, a->rd, a->rn, a->rm);
+ return do_zzz_fn(s, a, tcg_gen_gvec_xor);
}
static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
{
- return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
+ return do_zzz_fn(s, a, tcg_gen_gvec_andc);
}
/*
@@ -300,32 +305,32 @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a)
{
- return do_vector3_z(s, tcg_gen_gvec_add, a->esz, a->rd, a->rn, a->rm);
+ return do_zzz_fn(s, a, tcg_gen_gvec_add);
}
static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a)
{
- return do_vector3_z(s, tcg_gen_gvec_sub, a->esz, a->rd, a->rn, a->rm);
+ return do_zzz_fn(s, a, tcg_gen_gvec_sub);
}
static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a)
{
- return do_vector3_z(s, tcg_gen_gvec_ssadd, a->esz, a->rd, a->rn, a->rm);
+ return do_zzz_fn(s, a, tcg_gen_gvec_ssadd);
}
static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
{
- return do_vector3_z(s, tcg_gen_gvec_sssub, a->esz, a->rd, a->rn, a->rm);
+ return do_zzz_fn(s, a, tcg_gen_gvec_sssub);
}
static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a)
{
- return do_vector3_z(s, tcg_gen_gvec_usadd, a->esz, a->rd, a->rn, a->rm);
+ return do_zzz_fn(s, a, tcg_gen_gvec_usadd);
}
static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
{
- return do_vector3_z(s, tcg_gen_gvec_ussub, a->esz, a->rd, a->rn, a->rm);
+ return do_zzz_fn(s, a, tcg_gen_gvec_ussub);
}
/*
--
2.20.1
- [PULL 10/35] hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers, (continued)
- [PULL 10/35] hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers, Peter Maydell, 2020/08/28
- [PULL 11/35] hw/arm/xilinx_zynq: Uninline cadence_uart_create(), Peter Maydell, 2020/08/28
- [PULL 13/35] hw/qdev-clock: Uninline qdev_connect_clock_in(), Peter Maydell, 2020/08/28
- [PULL 12/35] hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize, Peter Maydell, 2020/08/28
- [PULL 14/35] hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize, Peter Maydell, 2020/08/28
- [PULL 16/35] hw/misc/unimp: Display the value with width of the access size, Peter Maydell, 2020/08/28
- [PULL 15/35] hw/misc/unimp: Display value after offset, Peter Maydell, 2020/08/28
- [PULL 17/35] hw/misc/unimp: Display the offset with width of the region size, Peter Maydell, 2020/08/28
- [PULL 18/35] armsse: Define ARMSSEClass correctly, Peter Maydell, 2020/08/28
- [PULL 19/35] qemu/int128: Add int128_lshift, Peter Maydell, 2020/08/28
- [PULL 21/35] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn,
Peter Maydell <=
- [PULL 22/35] target/arm: Rearrange {sve,fp}_check_access assert, Peter Maydell, 2020/08/28
- [PULL 20/35] target/arm: Split out gen_gvec_fn_zz, Peter Maydell, 2020/08/28
- [PULL 23/35] target/arm: Merge do_vector2_p into do_mov_p, Peter Maydell, 2020/08/28
- [PULL 24/35] target/arm: Clean up 4-operand predicate expansion, Peter Maydell, 2020/08/28
- [PULL 26/35] target/arm: Split out gen_gvec_ool_zzzp, Peter Maydell, 2020/08/28
- [PULL 25/35] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp, Peter Maydell, 2020/08/28
- [PULL 28/35] target/arm: Split out gen_gvec_ool_zzp, Peter Maydell, 2020/08/28
- [PULL 27/35] target/arm: Merge helper_sve_clr_* and helper_sve_movz_*, Peter Maydell, 2020/08/28
- [PULL 29/35] target/arm: Split out gen_gvec_ool_zzz, Peter Maydell, 2020/08/28
- [PULL 30/35] target/arm: Split out gen_gvec_ool_zz, Peter Maydell, 2020/08/28