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[PATCH v2 18/76] target/microblaze: Fix width of EDR
From: |
Richard Henderson |
Subject: |
[PATCH v2 18/76] target/microblaze: Fix width of EDR |
Date: |
Fri, 28 Aug 2020 07:18:31 -0700 |
The exception data register is only 32-bits wide. Do not use a
64-bit type to represent it. Since cpu_edr is only used during
MSR and MTR instructions, we can just as easily use an explicit
load and store, so eliminate the variable.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/cpu.h | 2 +-
target/microblaze/translate.c | 11 +++++------
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 72f068a5fd..b88acba12b 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -242,7 +242,7 @@ struct CPUMBState {
uint32_t esr;
uint32_t fsr;
uint32_t btr;
- uint64_t edr;
+ uint32_t edr;
float_status fp_status;
/* Stack protectors. Yes, it's a hw feature. */
uint32_t slr, shr;
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index a2bba0fe61..a862ac4055 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -59,7 +59,6 @@ static TCGv_i32 cpu_pc;
static TCGv_i32 cpu_msr;
static TCGv_i64 cpu_ear;
static TCGv_i32 cpu_esr;
-static TCGv_i64 cpu_edr;
static TCGv_i32 env_imm;
static TCGv_i32 env_btaken;
static TCGv_i32 cpu_btarget;
@@ -548,7 +547,8 @@ static void dec_msr(DisasContext *dc)
cpu_env, offsetof(CPUMBState, btr));
break;
case SR_EDR:
- tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]);
+ tcg_gen_st_i32(cpu_R[dc->ra],
+ cpu_env, offsetof(CPUMBState, edr));
break;
case 0x800:
tcg_gen_st_i32(cpu_R[dc->ra],
@@ -591,7 +591,8 @@ static void dec_msr(DisasContext *dc)
cpu_env, offsetof(CPUMBState, btr));
break;
case SR_EDR:
- tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr);
+ tcg_gen_ld_i32(cpu_R[dc->rd],
+ cpu_env, offsetof(CPUMBState, edr));
break;
case 0x800:
tcg_gen_ld_i32(cpu_R[dc->rd],
@@ -1818,7 +1819,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
/* Registers that aren't modeled are reported as 0 */
- qemu_fprintf(f, "redr=%" PRIx64 " rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 "
+ qemu_fprintf(f, "redr=%x rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 "
"rtlblo=0 rtlbhi=0\n", env->edr);
qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr);
for (i = 0; i < 32; i++) {
@@ -1868,8 +1869,6 @@ void mb_tcg_init(void)
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear");
cpu_esr =
tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr");
- cpu_edr =
- tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr");
}
void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb,
--
2.25.1
- Re: [PATCH v2 09/76] target/microblaze: Split out FSR from env->sregs, (continued)
- [PATCH v2 10/76] target/microblaze: Split out BTR from env->sregs, Richard Henderson, 2020/08/28
- [PATCH v2 11/76] target/microblaze: Split out EDR from env->sregs, Richard Henderson, 2020/08/28
- [PATCH v2 12/76] target/microblaze: Split the cpu_SR array, Richard Henderson, 2020/08/28
- [PATCH v2 13/76] target/microblaze: Fix width of PC and BTARGET, Richard Henderson, 2020/08/28
- [PATCH v2 14/76] target/microblaze: Fix width of MSR, Richard Henderson, 2020/08/28
- [PATCH v2 15/76] target/microblaze: Fix width of ESR, Richard Henderson, 2020/08/28
- [PATCH v2 16/76] target/microblaze: Fix width of FSR, Richard Henderson, 2020/08/28
- [PATCH v2 17/76] target/microblaze: Fix width of BTR, Richard Henderson, 2020/08/28
- [PATCH v2 18/76] target/microblaze: Fix width of EDR,
Richard Henderson <=
- [PATCH v2 19/76] target/microblaze: Remove cpu_ear, Richard Henderson, 2020/08/28
- [PATCH v2 20/76] target/microblaze: Tidy raising of exceptions, Richard Henderson, 2020/08/28
- [PATCH v2 21/76] target/microblaze: Mark raise_exception as noreturn, Richard Henderson, 2020/08/28
- [PATCH v2 22/76] target/microblaze: Remove helper_debug and env->debug, Richard Henderson, 2020/08/28
- [PATCH v2 24/76] target/microblaze: Tidy mb_tcg_init, Richard Henderson, 2020/08/28
- [PATCH v2 23/76] target/microblaze: Rename env_* tcg variables to cpu_*, Richard Henderson, 2020/08/28
- [PATCH v2 26/76] target/microblaze: Use DISAS_NORETURN, Richard Henderson, 2020/08/28
- [PATCH v2 25/76] target/microblaze: Split out MSR[C] to its own variable, Richard Henderson, 2020/08/28
- [PATCH v2 27/76] target/microblaze: Check singlestep_enabled in gen_goto_tb, Richard Henderson, 2020/08/28