Re: [RFC v4 23/70] target/riscv: rvv-1.0: load/store whole register instructions

[Richard Henderson]

On 8/17/20 1:49 AM, frank.chang@sifive.com wrote:
> +/*
> + * load and store whole register instructions ignore vtype and vl setting.
> + * Thus, we don't need to check vill bit. (Section 7.9)
> + */
> +#define GEN_LDST_WHOLE_TRANS(NAME, EEW, ARGTYPE, ARG_NF, IS_STORE)     \
> +static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE * a)           \
> +{                                                                      \
> +    if (require_rvv(s) &&                                              \
> +        QEMU_IS_ALIGNED(a->rd, ARG_NF)) {                              \
> +        uint32_t data = 0;                                             \
> +        bool ret;                                                      \
> +        data = FIELD_DP32(data, VDATA, NF, ARG_NF);                    \
> +        ret = ldst_whole_trans(a->rd, a->rs1, data, gen_helper_##NAME, \
> +                               s, IS_STORE);                           \
> +        return ret;                                                    \
> +    }                                                                  \
> +    return false;                                                      \
> +}

Decodetree is intentionally organized such that ARGTYPE = NAME.  There's no
point in duplicating that.  Move everything besides the call to
ldst_whole_trans into ldst_whole_trans.


r~