Re: [PATCH 05/12] hw/riscv: Move sifive

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Re: [PATCH 05/12] hw/riscv: Move sifive_clint model to hw/intc

From:	Alistair Francis
Subject:	Re: [PATCH 05/12] hw/riscv: Move sifive_clint model to hw/intc
Date:	Fri, 4 Sep 2020 10:30:19 -0700

On Thu, Sep 3, 2020 at 3:45 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_clint model to hw/intc directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  include/hw/{riscv => intc}/sifive_clint.h | 0
>  hw/{riscv => intc}/sifive_clint.c         | 2 +-
>  hw/riscv/microchip_pfsoc.c                | 2 +-
>  hw/riscv/sifive_e.c                       | 2 +-
>  hw/riscv/sifive_u.c                       | 2 +-
>  hw/riscv/spike.c                          | 2 +-
>  hw/riscv/virt.c                           | 2 +-
>  hw/intc/Kconfig                           | 3 +++
>  hw/intc/meson.build                       | 1 +
>  hw/riscv/Kconfig                          | 5 +++++
>  hw/riscv/meson.build                      | 1 -
>  11 files changed, 15 insertions(+), 7 deletions(-)
>  rename include/hw/{riscv => intc}/sifive_clint.h (100%)
>  rename hw/{riscv => intc}/sifive_clint.c (99%)
>
> diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/intc/sifive_clint.h
> similarity index 100%
> rename from include/hw/riscv/sifive_clint.h
> rename to include/hw/intc/sifive_clint.h
> diff --git a/hw/riscv/sifive_clint.c b/hw/intc/sifive_clint.c
> similarity index 99%
> rename from hw/riscv/sifive_clint.c
> rename to hw/intc/sifive_clint.c
> index fa1ddf2..0f41e5e 100644
> --- a/hw/riscv/sifive_clint.c
> +++ b/hw/intc/sifive_clint.c
> @@ -26,7 +26,7 @@
>  #include "hw/sysbus.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/qdev-properties.h"
> -#include "hw/riscv/sifive_clint.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "qemu/timer.h"
>
>  static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index da6bd29..131eea1 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -48,9 +48,9 @@
>  #include "hw/misc/unimp.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/microchip_pfsoc.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "sysemu/sysemu.h"
>
>  /*
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 7f43ed9..3bdb16e 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -40,10 +40,10 @@
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_plic.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_e.h"
>  #include "hw/riscv/boot.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "hw/misc/sifive_e_prci.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 7997537..7187d1a 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -47,10 +47,10 @@
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_plic.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_u.h"
>  #include "hw/riscv/boot.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "chardev/char.h"
>  #include "net/eth.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index b54a396..59d9d87 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -33,10 +33,10 @@
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_htif.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/spike.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/device_tree.h"
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index c67a910..bce2020 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -31,11 +31,11 @@
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_plic.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_test.h"
>  #include "hw/riscv/virt.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/device_tree.h"
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index 2ae1e89..f499d0f 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -67,3 +67,6 @@ config RX_ICU
>
>  config LOONGSON_LIOINTC
>      bool
> +
> +config SIFIVE_CLINT
> +    bool
> diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> index c16f7f0..1e20daa 100644
> --- a/hw/intc/meson.build
> +++ b/hw/intc/meson.build
> @@ -47,6 +47,7 @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: 
> files('rx_icu.c'))
>  specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
>  specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: 
> files('s390_flic_kvm.c'))
>  specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
> +specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: 
> files('sifive_clint.c'))
>  specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
>  specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
>  specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 5a8335b..f8bb7e7 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -15,6 +15,7 @@ config SIFIVE_E
>      bool
>      select HART
>      select SIFIVE
> +    select SIFIVE_CLINT
>      select SIFIVE_GPIO
>      select SIFIVE_E_PRCI
>      select UNIMP
> @@ -24,6 +25,7 @@ config SIFIVE_U
>      select CADENCE
>      select HART
>      select SIFIVE
> +    select SIFIVE_CLINT
>      select SIFIVE_GPIO
>      select SIFIVE_PDMA
>      select SIFIVE_U_OTP
> @@ -35,6 +37,7 @@ config SPIKE
>      select HART
>      select HTIF
>      select SIFIVE
> +    select SIFIVE_CLINT
>
>  config OPENTITAN
>      bool
> @@ -54,11 +57,13 @@ config RISCV_VIRT
>      select PCI_EXPRESS_GENERIC_BRIDGE
>      select PFLASH_CFI01
>      select SIFIVE
> +    select SIFIVE_CLINT
>
>  config MICROCHIP_PFSOC
>      bool
>      select HART
>      select SIFIVE
> +    select SIFIVE_CLINT
>      select UNIMP
>      select MCHP_PFSOC_MMUART
>      select SIFIVE_PDMA
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index 24177ef..ea72178 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
>  riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
>  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
>  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
> --
> 2.7.4
>
>

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Re: [PATCH 01/12] hw/riscv: Move sifive_e_prci model to hw/misc, (continued)
- [PATCH 02/12] hw/riscv: Move sifive_u_prci model to hw/misc, Bin Meng, 2020/09/03
  - Re: [PATCH 02/12] hw/riscv: Move sifive_u_prci model to hw/misc, Alistair Francis, 2020/09/04
- [PATCH 03/12] hw/riscv: Move sifive_u_otp model to hw/misc, Bin Meng, 2020/09/03
  - Re: [PATCH 03/12] hw/riscv: Move sifive_u_otp model to hw/misc, Alistair Francis, 2020/09/04
- [PATCH 04/12] hw/riscv: Move sifive_gpio model to hw/gpio, Bin Meng, 2020/09/03
  - Re: [PATCH 04/12] hw/riscv: Move sifive_gpio model to hw/gpio, Alistair Francis, 2020/09/04
- [PATCH 06/12] hw/riscv: Move sifive_plic model to hw/intc, Bin Meng, 2020/09/03
  - Re: [PATCH 06/12] hw/riscv: Move sifive_plic model to hw/intc, Alistair Francis, 2020/09/04
- [PATCH 05/12] hw/riscv: Move sifive_clint model to hw/intc, Bin Meng, 2020/09/03
  - Re: [PATCH 05/12] hw/riscv: Move sifive_clint model to hw/intc, Alistair Francis <=
- [PATCH 07/12] hw/riscv: Move riscv_htif model to hw/char, Bin Meng, 2020/09/03
  - Re: [PATCH 07/12] hw/riscv: Move riscv_htif model to hw/char, Alistair Francis, 2020/09/04
- [PATCH 08/12] hw/riscv: Move sifive_uart model to hw/char, Bin Meng, 2020/09/03
  - Re: [PATCH 08/12] hw/riscv: Move sifive_uart model to hw/char, Alistair Francis, 2020/09/04
- [PATCH 09/12] hw/riscv: Move sifive_test model to hw/misc, Bin Meng, 2020/09/03
  - Re: [PATCH 09/12] hw/riscv: Move sifive_test model to hw/misc, Alistair Francis, 2020/09/04
- [PATCH 10/12] hw/riscv: Always build riscv_hart.c, Bin Meng, 2020/09/03
  - Re: [PATCH 10/12] hw/riscv: Always build riscv_hart.c, Alistair Francis, 2020/09/04
- [PATCH 11/12] hw/riscv: Drop CONFIG_SIFIVE, Bin Meng, 2020/09/03
  - Re: [PATCH 11/12] hw/riscv: Drop CONFIG_SIFIVE, Alistair Francis, 2020/09/04

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