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[PATCH v3 47/81] target/arm: Implement SVE2 scatter store insns
From: |
Richard Henderson |
Subject: |
[PATCH v3 47/81] target/arm: Implement SVE2 scatter store insns |
Date: |
Fri, 18 Sep 2020 11:37:17 -0700 |
From: Stephen Long <steplong@quicinc.com>
Add decoding logic for SVE2 64-bit/32-bit scatter non-temporal
store insns.
64-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT1W (vector plus scalar)
* STNT1D (vector plus scalar)
32-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT1W (vector plus scalar)
Signed-off-by: Stephen Long <steplong@quicinc.com>
Message-Id: <20200422141553.8037-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sve.decode | 10 ++++++++++
target/arm/translate-sve.c | 8 ++++++++
2 files changed, 18 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index a375ce31f1..dc784dcabe 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1388,3 +1388,13 @@ UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... .....
@rda_rn_rm
CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=%reg_movprfx
SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx
+
+### SVE2 Memory Store Group
+
+# SVE2 64-bit scatter non-temporal store (vector plus scalar)
+STNT1_zprz 1110010 .. 00 ..... 001 ... ..... ..... \
+ @rprr_scatter_store xs=2 esz=3 scale=0
+
+# SVE2 32-bit scatter non-temporal store (vector plus scalar)
+STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \
+ @rprr_scatter_store xs=0 esz=2 scale=0
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 0d0e0c3b46..af8feff707 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -6172,6 +6172,14 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz
*a)
return true;
}
+static bool trans_STNT1_zprz(DisasContext *s, arg_ST1_zprz *a)
+{
+ if (!dc_isar_feature(aa64_sve2, s)) {
+ return false;
+ }
+ return trans_ST1_zprz(s, a);
+}
+
/*
* Prefetches
*/
--
2.25.1
- [PATCH v3 35/81] target/arm: Implement SVE2 bitwise ternary operations, (continued)
- [PATCH v3 35/81] target/arm: Implement SVE2 bitwise ternary operations, Richard Henderson, 2020/09/18
- [PATCH v3 36/81] target/arm: Implement SVE2 MATCH, NMATCH, Richard Henderson, 2020/09/18
- [PATCH v3 37/81] target/arm: Implement SVE2 saturating multiply-add long, Richard Henderson, 2020/09/18
- [PATCH v3 40/81] target/arm: Implement SVE2 complex integer multiply-add, Richard Henderson, 2020/09/18
- [PATCH v3 41/81] target/arm: Implement SVE2 ADDHNB, ADDHNT, Richard Henderson, 2020/09/18
- [PATCH v3 45/81] target/arm: Implement SVE2 HISTCNT, HISTSEG, Richard Henderson, 2020/09/18
- [PATCH v3 39/81] target/arm: Implement SVE2 integer multiply-add long, Richard Henderson, 2020/09/18
- [PATCH v3 38/81] target/arm: Implement SVE2 saturating multiply-add high, Richard Henderson, 2020/09/18
- [PATCH v3 42/81] target/arm: Implement SVE2 RADDHNB, RADDHNT, Richard Henderson, 2020/09/18
- [PATCH v3 46/81] target/arm: Implement SVE2 XAR, Richard Henderson, 2020/09/18
- [PATCH v3 47/81] target/arm: Implement SVE2 scatter store insns,
Richard Henderson <=
- [PATCH v3 43/81] target/arm: Implement SVE2 SUBHNB, SUBHNT, Richard Henderson, 2020/09/18
- [PATCH v3 52/81] target/arm: Pass separate addend to FCMLA helpers, Richard Henderson, 2020/09/18
- [PATCH v3 56/81] target/arm: Implement SVE2 integer multiply-add (indexed), Richard Henderson, 2020/09/18
- [PATCH v3 48/81] target/arm: Implement SVE2 gather load insns, Richard Henderson, 2020/09/18
- [PATCH v3 49/81] target/arm: Implement SVE2 FMMLA, Richard Henderson, 2020/09/18
- [PATCH v3 50/81] target/arm: Implement SVE2 SPLICE, EXT, Richard Henderson, 2020/09/18
- [PATCH v3 53/81] target/arm: Split out formats for 2 vectors + 1 index, Richard Henderson, 2020/09/18
- [PATCH v3 51/81] target/arm: Pass separate addend to {U, S}DOT helpers, Richard Henderson, 2020/09/18