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[RFC v5 64/68] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
From: |
frank . chang |
Subject: |
[RFC v5 64/68] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits |
Date: |
Wed, 30 Sep 2020 03:04:39 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
--
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 930607de24..ca78b7f352 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -92,7 +92,7 @@ typedef struct CPURISCVState CPURISCVState;
#include "pmp.h"
-#define RV_VLEN_MAX 256
+#define RV_VLEN_MAX 1024
FIELD(VTYPE, VLMUL, 0, 3)
FIELD(VTYPE, VSEW, 3, 3)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index db6c3d9bdf..576d20c6eb 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -631,8 +631,8 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1,
uint32_t data,
base = tcg_temp_new();
/*
- * As simd_desc supports at most 256 bytes, and in this implementation,
- * the max vector group length is 2048 bytes. So split it into two parts.
+ * As simd_desc supports at most 2048 bytes, and in this implementation,
+ * the max vector group length is 4096 bytes. So split it into two parts.
*
* The first part is vlen in bytes, encoded in maxsz of simd_desc.
* The second part is lmul, encoded in data of simd_desc.
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8d389af4b7..16331939b6 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -129,7 +129,7 @@ static uint32_t vext_wd(uint32_t desc)
static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
{
/*
- * As simd_desc support at most 256 bytes, the max vlen is 256 bits.
+ * As simd_desc support at most 2048 bytes, the max vlen is 1024 bits.
* so vlen in bytes (vlenb) is encoded as maxsz.
*/
uint32_t vlenb = simd_maxsz(desc);
--
2.17.1
- [RFC v5 54/68] target/riscv: rvv-1.0: single-width scaling shift instructions, (continued)
- [RFC v5 54/68] target/riscv: rvv-1.0: single-width scaling shift instructions, frank . chang, 2020/09/29
- [RFC v5 55/68] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 2020/09/29
- [RFC v5 56/68] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, frank . chang, 2020/09/29
- [RFC v5 57/68] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2020/09/29
- [RFC v5 58/68] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2020/09/29
- [RFC v5 59/68] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2020/09/29
- [RFC v5 60/68] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2020/09/29
- [RFC v5 61/68] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2020/09/29
- [RFC v5 62/68] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2020/09/29
- [RFC v5 63/68] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2020/09/29
- [RFC v5 64/68] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits,
frank . chang <=
- [RFC v5 65/68] target/riscv: gdb: modify gdb csr xml file to align with csr register map, frank . chang, 2020/09/29
- [RFC v5 66/68] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2020/09/29
- [RFC v5 68/68] target/riscv: trigger illegal instruction exception if frm is not valid, frank . chang, 2020/09/29
- [RFC v5 67/68] target/riscv: implement vstart CSR, frank . chang, 2020/09/29