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Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instruct
From: |
Peter Maydell |
Subject: |
Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions |
Date: |
Tue, 13 Oct 2020 18:12:29 +0100 |
On Tue, 13 Oct 2020 at 18:10, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 10/12/20 12:56 PM, Peter Maydell wrote:
> > On Mon, 12 Oct 2020 at 16:37, Peter Maydell <peter.maydell@linaro.org>
> > wrote:
> > This turns out not to work, because gen_jmp() always generates
> > a goto-tb for tb exit 0, and we hit the assert() that exit 0
> > was not used twice. Here's a fixup to fold into this patch:
>
> Indeed. I was going to suggest that here you should use arm_gen_condlabel()
> like you did for LE. Which I think would be still cleaner than your fixup
> patch.
I thought about that but it doesn't really fit, because
the condlabel is for "go to the next instruction
without having done anything". Here we need to do something
on that codepath (unlike LE).
thanks
-- PMM
- Re: [PATCH 09/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension, (continued)
[PATCH 10/10] target/arm: Fix writing to FPSCR.FZ16 on M-profile, Peter Maydell, 2020/10/12
[PATCH 05/10] target/arm: Don't allow BLX imm for M-profile, Peter Maydell, 2020/10/12
[PATCH 06/10] target/arm: Implement v8.1M branch-future insns (as NOPs), Peter Maydell, 2020/10/12
[PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions, Peter Maydell, 2020/10/12
Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions, Richard Henderson, 2020/10/13
[PATCH 08/10] target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile, Peter Maydell, 2020/10/12