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Re: [RFC PATCH 3/3] target/mips: Make the number of TLB entries a CPU pr

From: Philippe Mathieu-Daudé
Subject: Re: [RFC PATCH 3/3] target/mips: Make the number of TLB entries a CPU property
Date: Wed, 14 Oct 2020 12:54:18 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.3.1

On 10/14/20 12:20 PM, Jiaxun Yang wrote:
在 2020/10/13 21:25, Philippe Mathieu-Daudé 写道:
Allow changing the number of TLB entries for
testing/tunning purpose.

Example to force a 34Kf cpu with 64 TLB:

   $ qemu-system-mipsel -cpu 34Kf,tlb-entries=64 ...

This is helpful for developers of the Yocto Project [*]:

   Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit
   MIPS CI loop. It was observed that in this case CI test execution
   time was almost twice longer than 64bit MIPS variant that runs
   under MIPS64R2-generic model. It was investigated and concluded
   that the difference in number of TLBs 16 in 34Kf case vs 64 in
   MIPS64R2-generic is responsible for most of CI real time execution
   difference. Because with 16 TLBs linux user-land trashes TLB more
   and it needs to execute more instructions in TLB refill handler
   calls, as result it runs much longer.

[*] https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html

Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992
Reported-by: Victor Kamensky <kamensky@cisco.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Hi Philippe,

I think name can this property vtlb-entries?

MIPS R2 had introduced dual-TLB feature and the entries specified here
is the number of VTLB, while FTLB is another set of entries with fixed pagesize.

Although MIPS TCG haven't implemented dual-TLB but it can prevent future

Sure, good idea.

I'll follow Richard suggestion first, having a look at the P5600.


- Jiaxun

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