[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 22/44] hw/mips/r4k: Explicit CPU frequency is 200 MHz
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 22/44] hw/mips/r4k: Explicit CPU frequency is 200 MHz |
Date: |
Sat, 17 Oct 2020 16:02:21 +0200 |
Since its introduction in commit 6af0bf9c7c3,
the 'r4k' machine runs at 200 MHz.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-14-f4bug@amsat.org>
---
hw/mips/r4k.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/mips/r4k.c b/hw/mips/r4k.c
index 3487013a4a1..39bc626e7c5 100644
--- a/hw/mips/r4k.c
+++ b/hw/mips/r4k.c
@@ -13,6 +13,7 @@
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
+#include "hw/clock.h"
#include "hw/mips/mips.h"
#include "hw/mips/cpudevs.h"
#include "hw/intc/i8259.h"
@@ -182,6 +183,7 @@ void mips_r4k_init(MachineState *machine)
MemoryRegion *isa_io = g_new(MemoryRegion, 1);
MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
int bios_size;
+ Clock *cpuclk;
MIPSCPU *cpu;
CPUMIPSState *env;
ResetData *reset_info;
@@ -192,8 +194,11 @@ void mips_r4k_init(MachineState *machine)
DriveInfo *dinfo;
int be;
+ cpuclk = clock_new(OBJECT(machine), "cpu-refclk");
+ clock_set_hz(cpuclk, 200000000); /* 200 MHz */
+
/* init CPUs */
- cpu = MIPS_CPU(cpu_create(machine->cpu_type));
+ cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
env = &cpu->env;
reset_info = g_malloc0(sizeof(ResetData));
--
2.26.2
- [PULL 10/44] target/mips: Add loongson-ext lsdc2 group of instructions, (continued)
- [PULL 10/44] target/mips: Add loongson-ext lsdc2 group of instructions, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 13/44] target/mips/op_helper: Log unimplemented cache opcode, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 14/44] target/mips: Move cpu_mips_get_random() with CP0 helpers, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 15/44] target/mips/cp0_timer: Explicit unit in variable name, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 16/44] target/mips/cp0_timer: Document TIMER_PERIOD origin, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 17/44] target/mips: Move cp0_count_ns to CPUMIPSState, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 18/44] target/mips/cpu: Calculate the CP0 timer period using the CPU frequency, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 19/44] target/mips/cpu: Make cp0_count_rate a property, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 20/44] target/mips/cpu: Allow the CPU to use dynamic frequencies, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 21/44] target/mips/cpu: Introduce mips_cpu_create_with_clock() helper, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 22/44] hw/mips/r4k: Explicit CPU frequency is 200 MHz,
Philippe Mathieu-Daudé <=
- [PULL 23/44] hw/mips/fuloong2e: Set CPU frequency to 533 MHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 24/44] hw/mips/mipssim: Correct CPU frequency, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 25/44] hw/mips/jazz: Correct CPU frequencies, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 26/44] hw/mips/cps: Expose input clock and connect it to CPU cores, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 27/44] hw/mips/boston: Set CPU frequency to 1 GHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 28/44] hw/mips/malta: Set CPU frequency to 320 MHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 29/44] hw/mips/cps: Do not allow use without input clock, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 30/44] target/mips/cpu: Display warning when CPU is used without input clock, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 31/44] hw/mips/malta: Fix FPGA I/O region size, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 32/44] hw/mips/malta: Move gt64120 related code together, Philippe Mathieu-Daudé, 2020/10/17