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Re: [PATCH v2] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
From: |
Bin Meng |
Subject: |
Re: [PATCH v2] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry |
Date: |
Mon, 19 Oct 2020 09:57:55 +0800 |
Hi Ivan,
On Sat, Oct 17, 2020 at 1:10 AM Ivan Griffin <ivan.griffin@emdalo.com> wrote:
>
> Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU
> reporting a STORE/AMO Access Fault.
>
> This region is used by the PolarFire SoC port of U-Boot to
> interact with the FPGA system controller.
>
> Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com>
> ---
> hw/riscv/microchip_pfsoc.c | 10 ++++++++++
> include/hw/riscv/microchip_pfsoc.h | 1 +
> 2 files changed, 11 insertions(+)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 4627179cd3..9aaa276ee2 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -97,6 +97,7 @@ static const struct MemmapEntry {
> [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
> + [MICROCHIP_PFSOC_IOSCB_CTRL] = { 0x37020000, 0x1000 },
> [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
> [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
> };
> @@ -341,6 +342,15 @@ static void microchip_pfsoc_soc_realize(DeviceState
> *dev, Error **errp)
> create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
> memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
> memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
> +
> + /* IOSCBCTRL
> + *
> + * These registers are not documented in the official documentation
> + * but used by the polarfire-soc-bare-meta-library code
> + */
> + create_unimplemented_device("microchip.pfsoc.ioscb.ctrl",
> + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].base,
> + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].size);
> }
>
> static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
> diff --git a/include/hw/riscv/microchip_pfsoc.h
> b/include/hw/riscv/microchip_pfsoc.h
> index 8bfc7e1a85..3f1874b162 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -95,6 +95,7 @@ enum {
> MICROCHIP_PFSOC_ENVM_CFG,
> MICROCHIP_PFSOC_ENVM_DATA,
> MICROCHIP_PFSOC_IOSCB_CFG,
> + MICROCHIP_PFSOC_IOSCB_CTRL,
> MICROCHIP_PFSOC_DRAM,
> };
Thank you for the patch!
I am currently adding the DDR controller modeling support to PolarFire
SoC which will cover this memory map. With my patch series, your patch
is no longer needed.
Regards,
Bin
- [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry, Ivan Griffin, 2020/10/16
- Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry, Bin Meng, 2020/10/18
- Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry, Ivan Griffin, 2020/10/19
- Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry, Bin Meng, 2020/10/19
- Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry, Ivan Griffin, 2020/10/19