[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 05/13] hw/sd/sdhci: Resume pending DMA transfers on MMIO accesses
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 05/13] hw/sd/sdhci: Resume pending DMA transfers on MMIO accesses |
Date: |
Wed, 21 Oct 2020 19:34:42 +0200 |
If we have pending DMA requests scheduled, process them first.
So far we don't need to implement a bottom half to process them.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Message-Id: <20200903172806.489710-3-f4bug@amsat.org>
---
hw/sd/sdhci.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 61e469bd32f..4db77decf87 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -948,11 +948,21 @@ sdhci_buff_access_is_sequential(SDHCIState *s, unsigned
byte_num)
return true;
}
+static void sdhci_resume_pending_transfer(SDHCIState *s)
+{
+ timer_del(s->transfer_timer);
+ sdhci_data_transfer(s);
+}
+
static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
{
SDHCIState *s = (SDHCIState *)opaque;
uint32_t ret = 0;
+ if (timer_pending(s->transfer_timer)) {
+ sdhci_resume_pending_transfer(s);
+ }
+
switch (offset & ~0x3) {
case SDHC_SYSAD:
ret = s->sdmasysad;
@@ -1096,6 +1106,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
uint32_t value = val;
value <<= shift;
+ if (timer_pending(s->transfer_timer)) {
+ sdhci_resume_pending_transfer(s);
+ }
+
switch (offset & ~0x3) {
case SDHC_SYSAD:
s->sdmasysad = (s->sdmasysad & mask) | value;
--
2.26.2
- [PULL 00/13] SD/MMC patches for 2020-10-21, Philippe Mathieu-Daudé, 2020/10/21
- [PULL 01/13] hw/sd/sdhci: Fix qemu_log_mask() format string, Philippe Mathieu-Daudé, 2020/10/21
- [PULL 02/13] hw/sd/sdhci: Document the datasheet used, Philippe Mathieu-Daudé, 2020/10/21
- [PULL 03/13] hw/sd/sdhci: Fix DMA Transfer Block Size field, Philippe Mathieu-Daudé, 2020/10/21
- [PULL 04/13] hw/sd/sdhci: Stop multiple transfers when block count is cleared, Philippe Mathieu-Daudé, 2020/10/21
- [PULL 05/13] hw/sd/sdhci: Resume pending DMA transfers on MMIO accesses,
Philippe Mathieu-Daudé <=
- [PULL 06/13] hw/sd/sdhci: Let sdhci_update_irq() return if IRQ was delivered, Philippe Mathieu-Daudé, 2020/10/21
- [PULL 07/13] hw/sd/sdhci: Yield if interrupt delivered during multiple transfer, Philippe Mathieu-Daudé, 2020/10/21
- [PULL 08/13] hw/sd/sdcard: Add trace event for ERASE command (CMD38), Philippe Mathieu-Daudé, 2020/10/21
- [PULL 09/13] hw/sd/sdcard: Introduce the INVALID_ADDRESS definition, Philippe Mathieu-Daudé, 2020/10/21
- [PULL 10/13] hw/sd/sdcard: Do not use legal address '0' for INVALID_ADDRESS, Philippe Mathieu-Daudé, 2020/10/21
- [PULL 11/13] hw/sd/sdcard: Reset both start/end addresses on error, Philippe Mathieu-Daudé, 2020/10/21
- [PULL 12/13] hw/sd/sdcard: Do not attempt to erase out of range addresses, Philippe Mathieu-Daudé, 2020/10/21
- [PULL 13/13] hw/sd/sdcard: Assert if accessing an illegal group, Philippe Mathieu-Daudé, 2020/10/21
- Re: [PULL 00/13] SD/MMC patches for 2020-10-21, Peter Maydell, 2020/10/22