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Re: [PATCH v4 1/5] [RISCV_PM] Add J-extension into RISC-V
From: |
Alistair Francis |
Subject: |
Re: [PATCH v4 1/5] [RISCV_PM] Add J-extension into RISC-V |
Date: |
Wed, 21 Oct 2020 13:22:02 -0700 |
On Sat, Oct 17, 2020 at 12:15 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
> ---
> target/riscv/cpu.c | 4 ++++
> target/riscv/cpu.h | 2 ++
> 2 files changed, 6 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0bbfd7f457..fe6bab4a52 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> if (cpu->cfg.ext_h) {
> target_misa |= RVH;
> }
> + if (cpu->cfg.ext_j) {
> + target_misa |= RVJ;
> + }
> if (cpu->cfg.ext_v) {
> target_misa |= RVV;
> if (!is_power_of_2(cpu->cfg.vlen)) {
> @@ -516,6 +519,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
> /* This is experimental so mark with 'x-' */
> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> + DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
Usually you only want to allow the user to enable the extension at the
end of the series. That way if someone checks out QEMU between patch 1
and patch 5 they don't have a half working implementation (it will be
there, but they can't enable it).
Alistair
> DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index de275782e6..eca611a367 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -66,6 +66,7 @@
> #define RVS RV('S')
> #define RVU RV('U')
> #define RVH RV('H')
> +#define RVJ RV('J')
>
> /* S extension denotes that Supervisor mode exists, however it is possible
> to have a core that support S mode but does not have an MMU and there
> @@ -277,6 +278,7 @@ struct RISCVCPU {
> bool ext_s;
> bool ext_u;
> bool ext_h;
> + bool ext_j;
> bool ext_v;
> bool ext_counters;
> bool ext_ifencei;
> --
> 2.20.1
>
>
- [PATCH v4 0/5] RISC-V Pointer Masking implementation, Alexey Baturo, 2020/10/17
- [PATCH v4 2/5] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode, Alexey Baturo, 2020/10/17
- [PATCH v4 1/5] [RISCV_PM] Add J-extension into RISC-V, Alexey Baturo, 2020/10/17
- Re: [PATCH v4 1/5] [RISCV_PM] Add J-extension into RISC-V,
Alistair Francis <=
- [PATCH v4 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs, Alexey Baturo, 2020/10/17
- [PATCH v4 5/5] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension, Alexey Baturo, 2020/10/17
- [PATCH v4 4/5] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alexey Baturo, 2020/10/17