Re: [PATCH] i386/cpu: Expose the PTWRITE to the guest

[Paolo Bonzini]

On 22/10/20 06:01, Luwei Kang wrote:
> PTWRITE provides a mechanism by which software can instrument the
> Intel PT trace. The current implementation will mask off this
> feature when the PTWRITE is supported on the host because of the
> Intel PT CPUID is a constant value(ICX CPUID) in qemu. This patch
> will expose the PTWRITE feature to the guest.
> 
> Signed-off-by: Luwei Kang <luwei.kang@intel.com>
> ---
>  target/i386/cpu.c | 24 ++++++++++++++++++++++++
>  target/i386/cpu.h |  4 ++++
>  2 files changed, 28 insertions(+)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index aeabdd5bd4..242ba8a870 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -672,6 +672,7 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_t 
> vendor1,
>  #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
>            /* missing:
>            CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
> +#define TCG_14_0_EBX_FEATURES 0
>  #define TCG_14_0_ECX_FEATURES 0
>  
>  typedef enum FeatureWordType {
> @@ -1302,6 +1303,26 @@ static FeatureWordInfo 
> feature_word_info[FEATURE_WORDS] = {
>          }
>      },
>  
> +    [FEAT_14_0_EBX] = {
> +        .type = CPUID_FEATURE_WORD,
> +        .feat_names = {
> +            NULL, NULL, NULL, NULL,
> +            "ptwrite", NULL, NULL, NULL,
> +            NULL, NULL, NULL, NULL,
> +            NULL, NULL, NULL, NULL,
> +            NULL, NULL, NULL, NULL,
> +            NULL, NULL, NULL, NULL,
> +            NULL, NULL, NULL, NULL,
> +            NULL, NULL, NULL, NULL,
> +        },
> +        .cpuid = {
> +            .eax = 0x14,
> +            .needs_ecx = true, .ecx = 0,
> +            .reg = R_EBX,
> +        },
> +        .tcg_features = TCG_14_0_EBX_FEATURES,
> +    },
> +

Please add a dependency on the processor tracing flag too.

Paolo

>      [FEAT_14_0_ECX] = {
>          .type = CPUID_FEATURE_WORD,
>          .feat_names = {
> @@ -5764,6 +5785,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, 
> uint32_t count,
>              *eax = INTEL_PT_MAX_SUBLEAF;
>              *ebx = INTEL_PT_MINIMAL_EBX;
>              *ecx = INTEL_PT_MINIMAL_ECX;
> +            if (env->features[FEAT_14_0_EBX] & CPUID_14_0_EBX_PTWRITE) {
> +                *ebx |= CPUID_14_0_EBX_PTWRITE;
> +            }
>              if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) {
>                  *ecx |= CPUID_14_0_ECX_LIP;
>              }
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 1fcd93e39a..9fffe6eb6f 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -541,6 +541,7 @@ typedef enum FeatureWord {
>      FEAT_VMX_EPT_VPID_CAPS,
>      FEAT_VMX_BASIC,
>      FEAT_VMX_VMFUNC,
> +    FEAT_14_0_EBX,
>      FEAT_14_0_ECX,
>      FEATURE_WORDS,
>  } FeatureWord;
> @@ -798,6 +799,9 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
>  /* AVX512 BFloat16 Instruction */
>  #define CPUID_7_1_EAX_AVX512_BF16       (1U << 5)
>  
> +/* Intel PT support PTWRITE */
> +#define CPUID_14_0_EBX_PTWRITE          (1U << 4)
> +
>  /* Packets which contain IP payload have LIP values */
>  #define CPUID_14_0_ECX_LIP              (1U << 31)
>  
>