Re: [PATCH 1/2] riscv: Add sifive test device to sifive_e target

[Alistair Francis]

On Fri, Oct 23, 2020 at 2:45 PM Keith Packard via <qemu-devel@nongnu.org> wrote:
>
> The SiFive test device provides a mechanism for terminating the qemu
> instance from the emulated system. This patch adds that device to the
> sifive_e target.
>
> Signed-off-by: Keith Packard <keithp@keithp.com>
> ---
>  hw/riscv/sifive_e.c         | 4 ++++
>  include/hw/riscv/sifive_e.h | 1 +
>  2 files changed, 5 insertions(+)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index fcfac16816..417e3a5409 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -11,6 +11,7 @@
>   * 3) PRCI (Power, Reset, Clock, Interrupt)
>   * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM
>   * 5) Flash memory emulated as RAM
> + * 6) TEST (Test device)
>   *
>   * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.
>   * The OTP ROM and Flash boot code will be emulated in a future version.
> @@ -45,6 +46,7 @@
>  #include "hw/intc/sifive_clint.h"
>  #include "hw/intc/sifive_plic.h"
>  #include "hw/misc/sifive_e_prci.h"
> +#include "hw/misc/sifive_test.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/sysemu.h"
> @@ -57,6 +59,7 @@ static const struct MemmapEntry {
>      [SIFIVE_E_DEV_DEBUG] =    {        0x0,     0x1000 },
>      [SIFIVE_E_DEV_MROM] =     {     0x1000,     0x2000 },
>      [SIFIVE_E_DEV_OTP] =      {    0x20000,     0x2000 },
> +    [SIFIVE_E_DEV_TEST] =     {   0x100000,     0x1000 },

I don't see this mentioned in the FE310 data sheet. Is it included in
the hardware?

Alistair

>      [SIFIVE_E_DEV_CLINT] =    {  0x2000000,    0x10000 },
>      [SIFIVE_E_DEV_PLIC] =     {  0xc000000,  0x4000000 },
>      [SIFIVE_E_DEV_AON] =      { 0x10000000,     0x8000 },
> @@ -216,6 +219,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error 
> **errp)
>          memmap[SIFIVE_E_DEV_CLINT].size, 0, ms->smp.cpus,
>          SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
>          SIFIVE_CLINT_TIMEBASE_FREQ, false);
> +    sifive_test_create(memmap[SIFIVE_E_DEV_TEST].base);
>      create_unimplemented_device("riscv.sifive.e.aon",
>          memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size);
>      sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
> diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> index 83604da805..92bab6d0d4 100644
> --- a/include/hw/riscv/sifive_e.h
> +++ b/include/hw/riscv/sifive_e.h
> @@ -56,6 +56,7 @@ enum {
>      SIFIVE_E_DEV_DEBUG,
>      SIFIVE_E_DEV_MROM,
>      SIFIVE_E_DEV_OTP,
> +    SIFIVE_E_DEV_TEST,
>      SIFIVE_E_DEV_CLINT,
>      SIFIVE_E_DEV_PLIC,
>      SIFIVE_E_DEV_AON,
> --
> 2.28.0
>
>