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[PATCH v2 03/10] hw/riscv: microchip_pfsoc: Connect DDR memory controlle
From: |
Bin Meng |
Subject: |
[PATCH v2 03/10] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules |
Date: |
Wed, 28 Oct 2020 13:30:03 +0800 |
From: Bin Meng <bin.meng@windriver.com>
Connect DDR SGMII PHY module and CFG module to the PolarFire SoC.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
(no changes since v1)
hw/riscv/Kconfig | 1 +
hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++
include/hw/riscv/microchip_pfsoc.h | 5 +++++
3 files changed, 24 insertions(+)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 2df978f..c8e50bd 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -4,6 +4,7 @@ config IBEX
config MICROCHIP_PFSOC
bool
select CADENCE_SDHCI
+ select MCHP_PFSOC_DMC
select MCHP_PFSOC_MMUART
select MSI_NONBROKEN
select SIFIVE_CLINT
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 6aac849..3c504f7 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -15,6 +15,7 @@
* 4) Cadence eMMC/SDHC controller and an SD card connected to it
* 5) SiFive Platform DMA (Direct Memory Access Controller)
* 6) GEM (Gigabit Ethernet MAC Controller)
+ * 7) DMC (DDR Memory Controller)
*
* This board currently generates devicetree dynamically that indicates at
least
* two harts and up to five harts.
@@ -103,7 +104,9 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
+ [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 },
[MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
+ [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 },
[MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
@@ -149,6 +152,11 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma-controller", &s->dma,
TYPE_SIFIVE_PDMA);
+ object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy,
+ TYPE_MCHP_PFSOC_DDR_SGMII_PHY);
+ object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
+ TYPE_MCHP_PFSOC_DDR_CFG);
+
object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
@@ -278,6 +286,16 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev,
Error **errp)
memmap[MICROCHIP_PFSOC_MPUCFG].base,
memmap[MICROCHIP_PFSOC_MPUCFG].size);
+ /* DDR SGMII PHY */
+ sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0,
+ memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base);
+
+ /* DDR CFG */
+ sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0,
+ memmap[MICROCHIP_PFSOC_DDR_CFG].base);
+
/* SDHCI */
sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
diff --git a/include/hw/riscv/microchip_pfsoc.h
b/include/hw/riscv/microchip_pfsoc.h
index 8bfc7e1..5b81e26 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -24,6 +24,7 @@
#include "hw/char/mchp_pfsoc_mmuart.h"
#include "hw/dma/sifive_pdma.h"
+#include "hw/misc/mchp_pfsoc_dmc.h"
#include "hw/net/cadence_gem.h"
#include "hw/sd/cadence_sdhci.h"
@@ -37,6 +38,8 @@ typedef struct MicrochipPFSoCState {
RISCVHartArrayState e_cpus;
RISCVHartArrayState u_cpus;
DeviceState *plic;
+ MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
+ MchpPfSoCDdrCfgState ddr_cfg;
MchpPfSoCMMUartState *serial0;
MchpPfSoCMMUartState *serial1;
MchpPfSoCMMUartState *serial2;
@@ -82,7 +85,9 @@ enum {
MICROCHIP_PFSOC_MMUART0,
MICROCHIP_PFSOC_SYSREG,
MICROCHIP_PFSOC_MPUCFG,
+ MICROCHIP_PFSOC_DDR_SGMII_PHY,
MICROCHIP_PFSOC_EMMC_SD,
+ MICROCHIP_PFSOC_DDR_CFG,
MICROCHIP_PFSOC_MMUART1,
MICROCHIP_PFSOC_MMUART2,
MICROCHIP_PFSOC_MMUART3,
--
2.7.4
- [PATCH v2 00/10] hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box, Bin Meng, 2020/10/28
- [PATCH v2 01/10] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps, Bin Meng, 2020/10/28
- [PATCH v2 02/10] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support, Bin Meng, 2020/10/28
- [PATCH v2 03/10] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules,
Bin Meng <=
- [PATCH v2 05/10] hw/riscv: microchip_pfsoc: Connect the IOSCB module, Bin Meng, 2020/10/28
- [PATCH v2 04/10] hw/misc: Add Microchip PolarFire SoC IOSCB module support, Bin Meng, 2020/10/28
- [PATCH v2 06/10] hw/misc: Add Microchip PolarFire SoC SYSREG module support, Bin Meng, 2020/10/28
- [PATCH v2 07/10] hw/riscv: microchip_pfsoc: Connect the SYSREG module, Bin Meng, 2020/10/28
- [PATCH v2 08/10] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0, Bin Meng, 2020/10/28
- [PATCH v2 09/10] hw/riscv: microchip_pfsoc: Correct DDR memory map, Bin Meng, 2020/10/28
- [PATCH v2 10/10] hw/riscv: microchip_pfsoc: Hook the I2C1 controller, Bin Meng, 2020/10/28