[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v3 2/7] target/riscv: Add a virtualised MMU Mode
|
From: |
Alistair Francis |
|
Subject: |
Re: [PATCH v3 2/7] target/riscv: Add a virtualised MMU Mode |
|
Date: |
Tue, 3 Nov 2020 20:42:59 -0800 |
On Tue, Nov 3, 2020 at 12:20 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 11/3/20 11:50 AM, Alistair Francis wrote:
> > @@ -30,6 +30,10 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
> > #ifdef CONFIG_USER_ONLY
> > return 0;
> > #else
> > + if (riscv_cpu_virt_enabled(env)) {
> > + return env->priv | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
> > + }
>
> Still setting this bit here, incorrectly.
Argh! I must have dreamed fixing it. Sending a new version now.
Alistair
>
>
> r~
- [PATCH v3 0/7] Fix the Hypervisor access functions, Alistair Francis, 2020/11/03
- [PATCH v3 1/7] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit, Alistair Francis, 2020/11/03
- [PATCH v3 2/7] target/riscv: Add a virtualised MMU Mode, Alistair Francis, 2020/11/03
- [PATCH v3 3/7] target/riscv: Set the virtualised MMU mode when doing hyp accesses, Alistair Francis, 2020/11/03
- [PATCH v3 4/7] target/riscv: Remove the HS_TWO_STAGE flag, Alistair Francis, 2020/11/03
- [PATCH v3 5/7] target/riscv: Remove the hyp load and store functions, Alistair Francis, 2020/11/03
- [PATCH v3 6/7] target/riscv: Remove the Hypervisor access check function, Alistair Francis, 2020/11/03
- [PATCH v3 7/7] target/riscv: Split the Hypervisor execute load helpers, Alistair Francis, 2020/11/03