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[RFC 03/15] target/riscv: rvb: count bits set
From: |
frank . chang |
Subject: |
[RFC 03/15] target/riscv: rvb: count bits set |
Date: |
Wed, 18 Nov 2020 16:29:41 +0800 |
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
target/riscv/insn32-64.decode | 1 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
target/riscv/translate.c | 21 +++++++++++++++++++++
4 files changed, 35 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 250279e62ea..d5bea5af273 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -90,3 +90,4 @@ hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 011000000000 ..... 001 ..... 0011011 @r2
ctzw 011000000001 ..... 001 ..... 0011011 @r2
+pcntw 011000000010 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 884ed2a42fa..9e70a85d6f0 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -597,3 +597,4 @@ vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
# *** RV32B Standard Extension ***
clz 011000000000 ..... 001 ..... 0010011 @r2
ctz 011000000001 ..... 001 ..... 0010011 @r2
+pcnt 011000000010 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 1f02cb91a0a..6f1054e3908 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -29,6 +29,12 @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
return gen_cxz(ctx, a, &tcg_gen_ctzi_tl);
}
+static bool trans_pcnt(DisasContext *ctx, arg_pcnt *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &tcg_gen_ctpop_tl);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -44,4 +50,10 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
return gen_cxzw(ctx, a, &tcg_gen_ctzi_i32);
}
+static bool trans_pcntw(DisasContext *ctx, arg_pcntw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &gen_pcntw);
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 20b47f7a660..97e5899750e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -736,6 +736,12 @@ static bool gen_cxzw(DisasContext *ctx, arg_r2 *a,
return true;
}
+static void gen_pcntw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ tcg_gen_ctpop_tl(ret, arg1);
+}
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
@@ -793,6 +799,21 @@ static bool gen_cxz(DisasContext *ctx, arg_r2 *a,
return true;
}
+static bool gen_unary(DisasContext *ctx, arg_r2 *a,
+ void(*func)(TCGv, TCGv))
+{
+ TCGv source;
+ source = tcg_temp_new();
+
+ gen_get_gpr(source, a->rs1);
+
+ (*func)(source, source);
+
+ gen_set_gpr(a->rd, source);
+ tcg_temp_free(source);
+ return true;
+}
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.c.inc"
#include "insn_trans/trans_rvm.c.inc"
--
2.17.1
- [RFC 00/15] support subsets of bitmanip extension, frank . chang, 2020/11/18
- [RFC 01/15] target/riscv: reformat @sh format encoding for B-extension, frank . chang, 2020/11/18
- [RFC 02/15] target/riscv: rvb: count leading/trailing zeros, frank . chang, 2020/11/18
- [RFC 03/15] target/riscv: rvb: count bits set,
frank . chang <=
- [RFC 04/15] target/riscv: rvb: logic-with-negate, frank . chang, 2020/11/18
- [RFC 05/15] target/riscv: rvb: pack two words into one register, frank . chang, 2020/11/18
- [RFC 06/15] target/riscv: rvb: min/max instructions, frank . chang, 2020/11/18
- [RFC 07/15] target/riscv: rvb: sign-extend instructions, frank . chang, 2020/11/18
- [RFC 08/15] target/riscv: rvb: single-bit instructions, frank . chang, 2020/11/18