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Re: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from


From: Alistair Francis
Subject: Re: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line
Date: Thu, 19 Nov 2020 10:54:18 -0800

On Wed, Nov 18, 2020 at 12:45 AM <frank.chang@sifive.com> wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> B-extension is default off, use cpu rv32 or rv64 with x-b=true to
> enable B-extension.
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 4 ++++
>  target/riscv/cpu.h | 2 ++
>  2 files changed, 6 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0bbfd7f4574..bc29e118c6d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>          if (cpu->cfg.ext_h) {
>              target_misa |= RVH;
>          }
> +        if (cpu->cfg.ext_b) {
> +            target_misa |= RVB;
> +        }
>          if (cpu->cfg.ext_v) {
>              target_misa |= RVV;
>              if (!is_power_of_2(cpu->cfg.vlen)) {
> @@ -515,6 +518,7 @@ static Property riscv_cpu_properties[] = {
>      DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>      DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>      /* This is experimental so mark with 'x-' */
> +    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, true),
>      DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
>      DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
>      DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index de4705bb578..c1c77c58a87 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -66,6 +66,7 @@
>  #define RVS RV('S')
>  #define RVU RV('U')
>  #define RVH RV('H')
> +#define RVB RV('B')
>
>  /* S extension denotes that Supervisor mode exists, however it is possible
>     to have a core that support S mode but does not have an MMU and there
> @@ -278,6 +279,7 @@ struct RISCVCPU {
>          bool ext_f;
>          bool ext_d;
>          bool ext_c;
> +        bool ext_b;
>          bool ext_s;
>          bool ext_u;
>          bool ext_h;
> --
> 2.17.1
>
>



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