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[PATCH v2 17/28] target/arm: In v8.1M, don't set HFSR.FORCED on vector t
From: |
Peter Maydell |
Subject: |
[PATCH v2 17/28] target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures |
Date: |
Thu, 19 Nov 2020 21:56:06 +0000 |
In v8.1M, vector table fetch failures don't set HFSR.FORCED (see rule
R_LLRP). (In previous versions of the architecture this was either
required or IMPDEF.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/m_helper.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 721b4b4896e..9cdc8a64c29 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -722,11 +722,15 @@ load_fail:
* The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are
* secure); otherwise it targets the same security state as the
* underlying exception.
+ * In v8.1M HardFaults from vector table fetch fails don't set FORCED.
*/
if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
exc_secure = true;
}
- env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK;
+ env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK;
+ if (!arm_feature(env, ARM_FEATURE_V8_1M)) {
+ env->v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
+ }
armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secure);
return false;
}
--
2.20.1
- [PATCH v2 04/28] target/arm: Implement VSCCLRM insn, (continued)
- [PATCH v2 04/28] target/arm: Implement VSCCLRM insn, Peter Maydell, 2020/11/19
- [PATCH v2 06/28] target/arm: Enforce M-profile VMRS/VMSR register restrictions, Peter Maydell, 2020/11/19
- [PATCH v2 05/28] target/arm: Implement CLRM instruction, Peter Maydell, 2020/11/19
- [PATCH v2 07/28] target/arm: Refactor M-profile VMSR/VMRS handling, Peter Maydell, 2020/11/19
- [PATCH v2 08/28] target/arm: Move general-use constant expanders up in translate.c, Peter Maydell, 2020/11/19
- [PATCH v2 10/28] target/arm: Implement M-profile FPSCR_nzcvqc, Peter Maydell, 2020/11/19
- [PATCH v2 09/28] target/arm: Implement VLDR/VSTR system register, Peter Maydell, 2020/11/19
- [PATCH v2 14/28] target/arm: Implement FPCXT_NS fp system register, Peter Maydell, 2020/11/19
- [PATCH v2 12/28] target/arm: Factor out preserve-fp-state from full_vfp_access_check(), Peter Maydell, 2020/11/19
- [PATCH v2 17/28] target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures,
Peter Maydell <=
- [PATCH v2 13/28] target/arm: Implement FPCXT_S fp system register, Peter Maydell, 2020/11/19
- [PATCH v2 11/28] target/arm: Use new FPCR_NZCV_MASK constant, Peter Maydell, 2020/11/19
- [PATCH v2 16/28] target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry, Peter Maydell, 2020/11/19
- [PATCH v2 15/28] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M, Peter Maydell, 2020/11/19
- [PATCH v2 18/28] target/arm: Implement v8.1M REVIDR register, Peter Maydell, 2020/11/19
- [PATCH v2 19/28] target/arm: Implement new v8.1M NOCP check for exception return, Peter Maydell, 2020/11/19
- [PATCH v2 21/28] hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN, Peter Maydell, 2020/11/19
- [PATCH v2 20/28] target/arm: Implement new v8.1M VLLDM and VLSTM encodings, Peter Maydell, 2020/11/19
- [PATCH v2 24/28] hw/intc/armv7m_nvic: Fix "return from inactive handler" check, Peter Maydell, 2020/11/19
- [PATCH v2 22/28] hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit, Peter Maydell, 2020/11/19