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[Bug 1905356] [NEW] No check for unaligned data access in ARM32 instruct
From: |
JIANG Muhui |
Subject: |
[Bug 1905356] [NEW] No check for unaligned data access in ARM32 instructions |
Date: |
Tue, 24 Nov 2020 05:05:03 -0000 |
Public bug reported:
hi
According to the ARM documentation, there are alignment requirements of
load/store instructions. Alignment fault should be raised if the
alignment check is failed. However, it seems that QEMU doesn't implement
this, which is against the documentation of ARM. For example, the
instruction LDRD/STRD/LDREX/STREX must check the address is word
alignment no matter what value the SCTLR.A is.
I attached a testcase, which contains an instruction at VA 0x10240: ldrd
r0,[pc.#1] in the main function. QEMU can successfully load the data in
the unaligned address. The test is done in QEMU 5.1.0. I can provide
more testcases for the other instructions if you need. Many thanks.
To patch this, we need a check while we translate the instruction to
tcg. If the address is unaligned, a signal number (i.e., SIGBUS) should
be raised.
Regards
Muhui
** Affects: qemu
Importance: Undecided
Status: New
** Attachment added: "case_ldrd_arm"
https://bugs.launchpad.net/bugs/1905356/+attachment/5437364/+files/case_ldrd_arm
** Description changed:
hi
According to the ARM documentation, there are alignment requirements of
load/store instructions. Alignment fault should be raised if the
alignment check is failed. However, it seems that QEMU doesn't implement
this, which is against the documentation of ARM. For example, the
instruction LDRD/STRD/LDREX/STREX must check the address is word
alignment no matter what value the SCTLR.A is.
- I attached a testcase, which contains a instruction at VA 0x10240: ldrd
+ I attached a testcase, which contains an instruction at VA 0x10240: ldrd
r0,[pc.#1] in the main function. QEMU can successfully load the data in
the unaligned address. The test is done in QEMU 5.1.0. I can provide
more testcases for the other instructions if you need. Many thanks.
To patch this, we need a check while we translate the instruction to
tcg. If the address is unaligned, a signal number (i.e., SIGBUS) should
be raised.
Regards
Muhui
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https://bugs.launchpad.net/bugs/1905356
Title:
No check for unaligned data access in ARM32 instructions
Status in QEMU:
New
Bug description:
hi
According to the ARM documentation, there are alignment requirements
of load/store instructions. Alignment fault should be raised if the
alignment check is failed. However, it seems that QEMU doesn't
implement this, which is against the documentation of ARM. For
example, the instruction LDRD/STRD/LDREX/STREX must check the address
is word alignment no matter what value the SCTLR.A is.
I attached a testcase, which contains an instruction at VA 0x10240:
ldrd r0,[pc.#1] in the main function. QEMU can successfully load the
data in the unaligned address. The test is done in QEMU 5.1.0. I can
provide more testcases for the other instructions if you need. Many
thanks.
To patch this, we need a check while we translate the instruction to
tcg. If the address is unaligned, a signal number (i.e., SIGBUS)
should be raised.
Regards
Muhui
To manage notifications about this bug go to:
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- [Bug 1905356] [NEW] No check for unaligned data access in ARM32 instructions,
JIANG Muhui <=
- [Bug 1905356] Re: No check for unaligned data access in ARM32 instructions, Richard Henderson, 2020/11/24
- [Bug 1905356] Re: No check for unaligned data access in ARM32 instructions, Richard Henderson, 2020/11/24
- [Bug 1905356] Re: No check for unaligned data access in ARM32 instructions, JIANG Muhui, 2020/11/24
- [Bug 1905356] Re: No check for unaligned data access in ARM32 instructions, Richard Henderson, 2020/11/24
- [Bug 1905356] Re: No check for unaligned data access in ARM32 instructions, Richard Henderson, 2020/11/24